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revert 5af8f40d8f2c
[gem5.git]
/
src
/
arch
/
mips
/
isa.hh
2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
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2015-07-26
Nilay Vaish
cpu: implements vector registers
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2015-02-16
Andreas Hansson
arch: Make readMiscRegNoEffect const throughout
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2014-10-16
Andreas Hansson
arch: Use shared_ptr for all Faults
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2014-01-24
Andreas Hansson
arch: Make all register index flattening const
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2014-01-24
Ali Saidi
arch, cpu: Add support for flattening misc register...
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2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
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2013-02-19
Andreas Hansson
scons: Add warning for overloaded virtual functions
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2013-01-13
Nilay Vaish
x86: Changes to decoder, corrects 9376
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2013-01-07
Andreas Sandberg
arch: Move the ISA object to a separate section
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2013-01-07
Andreas Sandberg
arch: Make the ISA class inherit from SimObject
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2012-08-28
Andreas Hansson
Clock: Add a Cycles wrapper class and use where applicable
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2011-04-15
Nathan Binkert
includes: sort all includes
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2011-03-26
Korey Sewell
mips: cleanup ISA-specific code
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2011-02-04
Gabe Black
Fault: Rename sim/fault.hh to fault_fwd.hh to distingui...
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2010-09-14
Gabe Black
Faults: Pass the StaticInst involved, if any, to a...
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2010-01-22
Derek Hower
Automated merge with ssh://hg@m5sim.org/m5
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2010-01-19
Derek Hower
merge
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2009-12-31
Gabe Black
MIPS: Extract CPU pointer from the thread context in...
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2009-10-18
Brad Beckmann
merged with ISA event manager fix
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2009-10-17
Gabe Black
ISA: Fix compilation.
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2009-07-13
Derek Hower
merge
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2009-07-10
Gabe Black
MIPS: Fold the MiscRegFile all the way into the ISA...
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2009-07-09
Gabe Black
Get rid of the unused get(Data|Inst)Asid and (inst...
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2009-07-09
Gabe Black
Registers: Collapse ARM and MIPS regfile directories.
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2009-07-09
Gabe Black
Registers: Add an ISA object which replaces the MiscReg...
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