revert 5af8f40d8f2c
[gem5.git] / src / arch / mips / isa.hh
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout
2014-10-16 Andreas Hanssonarch: Use shared_ptr for all Faults
2014-01-24 Andreas Hanssonarch: Make all register index flattening const
2014-01-24 Ali Saidiarch, cpu: Add support for flattening misc register...
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-02-19 Andreas Hanssonscons: Add warning for overloaded virtual functions
2013-01-13 Nilay Vaishx86: Changes to decoder, corrects 9376
2013-01-07 Andreas Sandbergarch: Move the ISA object to a separate section
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-26 Korey Sewellmips: cleanup ISA-specific code
2011-02-04 Gabe BlackFault: Rename sim/fault.hh to fault_fwd.hh to distingui...
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-01-22 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2010-01-19 Derek Howermerge
2009-12-31 Gabe BlackMIPS: Extract CPU pointer from the thread context in...
2009-10-18 Brad Beckmannmerged with ISA event manager fix
2009-10-17 Gabe BlackISA: Fix compilation.
2009-07-13 Derek Howermerge
2009-07-10 Gabe BlackMIPS: Fold the MiscRegFile all the way into the ISA...
2009-07-09 Gabe BlackGet rid of the unused get(Data|Inst)Asid and (inst...
2009-07-09 Gabe BlackRegisters: Collapse ARM and MIPS regfile directories.
2009-07-09 Gabe BlackRegisters: Add an ISA object which replaces the MiscReg...