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arch,cpu: Add a setThreadContext method to the ISA class.
[gem5.git]
/
src
/
arch
/
power
/
isa.hh
2020-06-12
Gabe Black
arch,cpu: Add a setThreadContext method to the ISA...
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2020-02-26
Bobby R. Bruce
misc: merge branch 'release-staging-v19.0.0.0' into...
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2020-02-24
Bobby R. Bruce
misc: Merged release-staging-v19.0.0.0 into develop
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2020-02-19
Adrian Herrera
misc: pass ThreadContext on ISA clear
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2020-02-18
Gabe Black
power: Delete the authors lists from the power ISA.
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2020-02-05
Gabe Black
arch: Introduce a base class for ISA classes.
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2019-01-31
Gabe Black
power: Get rid of some ISA specific register types.
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2019-01-30
Giacomo Gabrielli
arch,cpu: Add vector predicate registers
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2019-01-22
Gabe Black
arch: cpu: Stop passing around misc registers by reference.
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2017-12-04
Gabe Black
misc: Rename misc.(hh|cc) to logging.(hh|cc)
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Added interface for vector reg file
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Simplify the rename interface and use RegId
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2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
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2015-07-26
Nilay Vaish
cpu: implements vector registers
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2015-02-16
Andreas Hansson
arch: Make readMiscRegNoEffect const throughout
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2014-01-24
Andreas Hansson
arch: Make all register index flattening const
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2014-01-24
Ali Saidi
arch, cpu: Add support for flattening misc register...
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2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
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2013-02-19
Andreas Hansson
scons: Add warning for overloaded virtual functions
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2013-01-13
Nilay Vaish
x86: Changes to decoder, corrects 9376
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2013-01-07
Andreas Sandberg
arch: Move the ISA object to a separate section
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2013-01-07
Andreas Sandberg
arch: Make the ISA class inherit from SimObject
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2011-01-03
Steve Reinhardt
Make commenting on close namespace brackets consistent.
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2010-01-19
Derek Hower
merge
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2009-10-27
Timothy M. Jones
POWER: Add support for the Power ISA
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