arch: cpu: Rename *FloatRegBits* to *FloatReg*.
[gem5.git] / src / arch / power / registers.hh
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*.
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-24 Gabe Blackbase: arch: Get rid of the now unused FloatRegVal type.
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa...
2018-10-17 Gabe Blackarch: Get rid of the unused type AnyReg.
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2017-07-05 Nathanael Premillieuarch, cpu: Architectural Register structural indexing
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-10-15 Steve Reinhardtcpu: rename *_DepTag constants to *_Reg_Base
2012-06-08 Andreas HanssonPower: Fix MaxMiscDestRegs which was set to zero
2012-06-05 Ali SaidiO3: Clean up the O3 structures and try to pack them...
2012-04-23 Gabe BlackISA: Put parser generated files in a "generated" directory.
2011-01-03 Steve ReinhardtMake commenting on close namespace brackets consistent.
2010-08-26 Min Kyu JeongARM: Fixed register flattening logic (FP_Base_DepTag...
2010-01-19 Derek Howermerge
2009-10-27 Timothy M. JonesPOWER: Add support for the Power ISA