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arch: cpu: Rename *FloatRegBits* to *FloatReg*.
[gem5.git]
/
src
/
arch
/
power
/
registers.hh
2019-01-31
Gabe Black
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
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2019-01-30
Giacomo Gabrielli
arch,cpu: Add vector predicate registers
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2019-01-24
Gabe Black
base: arch: Get rid of the now unused FloatRegVal type.
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2019-01-16
Gabe Black
arch: Make the ISA register types aliases for the globa...
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2018-10-17
Gabe Black
arch: Get rid of the unused type AnyReg.
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Added interface for vector reg file
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2017-07-05
Nathanael Premillieu
arch, cpu: Architectural Register structural indexing
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2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
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2015-07-26
Nilay Vaish
cpu: implements vector registers
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2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
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2013-10-15
Steve Reinhardt
cpu: rename *_DepTag constants to *_Reg_Base
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2012-06-08
Andreas Hansson
Power: Fix MaxMiscDestRegs which was set to zero
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2012-06-05
Ali Saidi
O3: Clean up the O3 structures and try to pack them...
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2012-04-23
Gabe Black
ISA: Put parser generated files in a "generated" directory.
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2011-01-03
Steve Reinhardt
Make commenting on close namespace brackets consistent.
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2010-08-26
Min Kyu Jeong
ARM: Fixed register flattening logic (FP_Base_DepTag...
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2010-01-19
Derek Hower
merge
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2009-10-27
Timothy M. Jones
POWER: Add support for the Power ISA
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