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cpu: Add HTM ExecContext API
[gem5.git] / src / arch / riscv /
2020-09-02 Gabe Blackmisc: Remove the "fault" parameter from syscall functions. tree | commitdiff
2020-08-28 Gabe Blackmisc: Clean up usage of arch/isa_traits.hh. tree | commitdiff
2020-08-28 Ian Jiangarch-riscv: Fix disassembling of jalr tree | commitdiff
2020-08-28 Gabe Blackriscv: Remove unnecessary includes from arch/riscv... tree | commitdiff
2020-08-26 Emily Brickeyarch: update port terminology tree | commitdiff
2020-08-25 Gabe Blackarch,cpu,sim: Get rid of the microcode ROM stub code. tree | commitdiff
2020-08-24 Emily Brickeyarch-riscv, arch-x86: convert tlb to new style stats tree | commitdiff
2020-08-21 Ian Jiangarch-riscv: Add float registers in copyRegs tree | commitdiff
2020-08-20 Gabe Blackarch: Eliminate the unused HasUnalignedMemAcc constant. tree | commitdiff
2020-08-20 Gabe Blackarch: Eliminate an unused pair of constants from isa_tr... tree | commitdiff
2020-08-20 Gabe Blackarch: Create a base class for decoders. tree | commitdiff
2020-08-19 Ian Jiangarch-riscv: Fix disassembling of CSR instructions tree | commitdiff
2020-08-18 Ian Jiangarch-riscv: Fix disassembling of all register instructions tree | commitdiff
2020-08-05 Gabe Blackarch: Use VPtr for uname. tree | commitdiff
2020-08-01 Ian Jiangarch-riscv: Fix disassembling of float register instruc... tree | commitdiff
2020-07-11 Gabe Blackarch,cpu: Consolidate most of the StackTrace classes... tree | commitdiff
2020-07-07 Gabe Blackarch: Delete the unused ProcessInfo class. tree | commitdiff
2020-07-04 Bobby R. Brucemisc: Merged m5ops_base hotfix into develop tree | commitdiff
2020-06-17 Gabe Blackarch,cpu,sim: Eliminate the now empty kernel statistics... tree | commitdiff
2020-06-12 Gabe Blackarch,cpu: Add a setThreadContext method to the ISA... tree | commitdiff
2020-06-11 Gabe Blackarch,cpu: Change setCPU to setThreadContext in Interrupts. tree | commitdiff
2020-06-09 Gabe Blackarch,cpu,dev,sim,mem: Collect System thread elements... tree | commitdiff
2020-06-09 Gabe Blackarch,base,cpu,kerm,sim: Build a symbol table for object... tree | commitdiff
2020-06-08 Bobby R. Brucemisc: Merge hotfix v20.0.0.2 into develop tree | commitdiff
2020-06-02 Bobby R. Brucemisc: Merge branch version update into develop tree | commitdiff
2020-06-02 Bobby R. Brucemisc: Merge in 'hotfix-m5-tick-rounding-error' tree | commitdiff
2020-05-28 Bobby R. BruceMerge branch 'release-staging-v20.0.0.0' into develop tree | commitdiff
2020-05-28 Bobby R. Brucemisc: Merge branch 'release-staging-v20.0.0.0' into... tree | commitdiff
2020-05-27 Bobby R. Brucearch-riscv,misc: Added M5_VAR_USED to MiscRegNames tree | commitdiff
2020-05-19 Gabe Blackarch,base,cpu,kern,sim: Encapsulate symbols in a class. tree | commitdiff
2020-05-11 Ayaz Akramarch-riscv,tests: small update to make gem5.fast compile tree | commitdiff
2020-05-02 Nils Asmussenarch-riscv: be prepared for CSR changes during PT walk. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: report that we don't have debugging support. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: respect IALIGN, influenced by toggling... tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: let FPU instructions fault if status.FS... tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: make uret,sret,mret SerializeAfter,NonSpecu... tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: make accesses to CSRs SerializeAfter. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: fault according to status.{TVM,TSK,TW}. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: added dummy implementation of wfi instruction. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: fault on mstatus accesses from lower privil... tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: ignore writes to SXL/UXL fields in status... tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: added (un)serialization of miscRegFile. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: show names of MiscRegs on accesses. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: fixed read of {M,S,U}TVEC. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: fixed formatting. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: implement RemoteGDB::acc for FS mode. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: implement sfence.vma to flush TLBs. tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: make sure only supported modes can be set... tree | commitdiff
2020-04-29 Nils Asmussenarch-riscv: added TLB and page table walker. tree | commitdiff
2020-04-22 Gabe Blackbase,arch,sim,cpu: Move object file loader components... tree | commitdiff
2020-04-22 Gabe Blackconfigs,arch,sim: Move fixFuncEventAddr into the Worklo... tree | commitdiff
2020-04-22 Gabe Blackarch,sim,kern,dev,cpu: Create a Workload SimObject. tree | commitdiff
2020-03-27 Gabe Blackriscv: Fix RISCV builds by updating its use of pseudoIn... tree | commitdiff
2020-03-26 Nils Asmussenarch-riscv: print information about faults. tree | commitdiff
2020-03-26 Nils Asmussenarch-riscv: added support for pseudo instructions. tree | commitdiff
2020-03-25 Matthew Porembasim-se: Switch to new MemState API tree | commitdiff
2020-03-25 Matthew Porembasim-se: Extend MemState API to use VMAs tree | commitdiff
2020-03-20 Gabe Blackarch,sim: Merge Process::syscall and Process::getDesc. tree | commitdiff
2020-03-20 Gabe Blackarch,sim: Drop the syscall number from the syscall... tree | commitdiff
2020-03-20 Gabe Blackarch,sim: Create a common structure to hold syscall... tree | commitdiff
2020-03-19 Gabe Blackarch,cpu,mem,sim: Reimplement the SE translating proxy... tree | commitdiff
2020-03-19 Gabe Blackarch: Eliminate vtophys and its switching header file. tree | commitdiff
2020-03-19 Gabe Blackriscv: Implement translateFunctional. tree | commitdiff
2020-03-17 Gabe Blackkern,arch: Refactor SkipFuncEvent to not use skipFunction. tree | commitdiff
2020-03-12 Gabe Blackarch,sim: Get rid of the now unused setSyscallReturn... tree | commitdiff
2020-03-12 Gabe Blacksim: Get rid of the now unused getSyscallArg method. tree | commitdiff
2020-03-12 Gabe Blackriscv: Use a riscv specific GuestABI for riscv system... tree | commitdiff
2020-03-12 Gabe Blackriscv: Convert RISCV specific syscalls to Guest ABI. tree | commitdiff
2020-03-12 Gabe Blackarch,sim: Convert clone to GuestABI and define a cloneB... tree | commitdiff
2020-03-11 Gabe Blackconfig,arch,cpu,kern,sim: Extract kernel information... tree | commitdiff
2020-03-10 Giacomo Travaglinimisc: string.join has been removed in python3 tree | commitdiff
2020-03-09 Gabe Blackarch,cpu: Get rid of unused/unimplemented vtophys variants. tree | commitdiff
2020-03-04 Gabe Blackarch,cpu,mem: Replace the mmmapped IPR mechanism with... tree | commitdiff
2020-02-26 Bobby R. Brucemisc: merge branch 'release-staging-v19.0.0.0' into... tree | commitdiff
2020-02-24 Bobby R. Brucemisc: Merged release-staging-v19.0.0.0 into develop tree | commitdiff
2020-02-19 Adrian Herreramisc: pass ThreadContext on ISA clear tree | commitdiff
2020-02-18 Gabe Blackriscv: Delete authors lists from riscv files. tree | commitdiff
2020-02-11 Gabe Blackarch: Get rid of the generic mmapped IPR mechanism. tree | commitdiff
2020-02-10 Gabe Blackriscv: Cast to float explicitly when comparing a float... tree | commitdiff
2020-02-10 Gabe Blackarch: Add a bunch of missing override specifiers. tree | commitdiff
2020-02-08 Gabe Blackarch,sim: Replace setuidFunc with ignoreFunc. tree | commitdiff
2020-02-08 Gabe Blackarch: Switch SyscallDescABI in for SyscallDesc. tree | commitdiff
2020-02-08 Gabe Blackarch: Simplify the SyscallDesc tables. tree | commitdiff
2020-02-05 Gabe Blackarch: Introduce a base class for ISA classes. tree | commitdiff
2020-02-01 Gabe Blackarch,sim: Merge initCPU into the ISA System classes. tree | commitdiff
2020-02-01 Gabe Blackarch,sim: Merge initCPU and startupCPU. tree | commitdiff
2019-12-10 Gabe Blacksim,arch: Collapse the ISA specific versions of m5Syscall. tree | commitdiff
2019-12-10 Gabe Blackarch,cpu,sim: Push syscall number determination up... tree | commitdiff
2019-12-10 Gabe Blackarch: Get rid of the now unused setSyscallArg. tree | commitdiff
2019-12-10 Gabe Blackarch: Use ignoreWarnOnceFunc instead of the WarnOnce... tree | commitdiff
2019-12-08 Alec Roelkearch-riscv: set MaxMiscDestRegs to 2 tree | commitdiff
2019-12-01 Ian Jiangarch-riscv: Fix disassembling of immediate for c.lui... tree | commitdiff
2019-11-26 Ian Jiangarch-riscv: Fix immediate decoding for integer shift... tree | commitdiff
2019-11-26 Ian Jiangarch-riscv: Fix disassembling for fence and fence.i tree | commitdiff
2019-11-25 Ian Jiangarch-riscv: Fix disassembling for atomic instructions tree | commitdiff
2019-11-25 Ian Jiangarch-riscv: Fix disassembling of operand list for compr... tree | commitdiff
2019-11-25 Ian Jiangarch-riscv: Fix disassembling of immediate for U-type... tree | commitdiff
2019-11-22 IanJiangICTarch-riscv: Fix bug in serialize and unserialize of... tree | commitdiff
2019-11-18 Gabe Blackarch: Get rid of the (Big|Little)EndianGuest namespaces. tree | commitdiff
2019-11-18 Gabe Blackarch: Make and use endian specific versions of the... tree | commitdiff
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