2020-08-18 |
Ian Jiang | arch-riscv: Fix disassembling of all register instructions |
tree | commitdiff |
2020-08-05 |
Gabe Black | arch: Use VPtr for uname. |
tree | commitdiff |
2020-08-01 |
Ian Jiang | arch-riscv: Fix disassembling of float register instruc... |
tree | commitdiff |
2020-07-11 |
Gabe Black | arch,cpu: Consolidate most of the StackTrace classes... |
tree | commitdiff |
2020-07-07 |
Gabe Black | arch: Delete the unused ProcessInfo class. |
tree | commitdiff |
2020-07-04 |
Bobby R. Bruce | misc: Merged m5ops_base hotfix into develop |
tree | commitdiff |
2020-06-17 |
Gabe Black | arch,cpu,sim: Eliminate the now empty kernel statistics... |
tree | commitdiff |
2020-06-12 |
Gabe Black | arch,cpu: Add a setThreadContext method to the ISA... |
tree | commitdiff |
2020-06-11 |
Gabe Black | arch,cpu: Change setCPU to setThreadContext in Interrupts. |
tree | commitdiff |
2020-06-09 |
Gabe Black | arch,cpu,dev,sim,mem: Collect System thread elements... |
tree | commitdiff |
2020-06-09 |
Gabe Black | arch,base,cpu,kerm,sim: Build a symbol table for object... |
tree | commitdiff |
2020-06-08 |
Bobby R. Bruce | misc: Merge hotfix v20.0.0.2 into develop |
tree | commitdiff |
2020-06-02 |
Bobby R. Bruce | misc: Merge branch version update into develop |
tree | commitdiff |
2020-06-02 |
Bobby R. Bruce | misc: Merge in 'hotfix-m5-tick-rounding-error' |
tree | commitdiff |
2020-05-28 |
Bobby R. Bruce | Merge branch 'release-staging-v20.0.0.0' into develop |
tree | commitdiff |
2020-05-28 |
Bobby R. Bruce | misc: Merge branch 'release-staging-v20.0.0.0' into... |
tree | commitdiff |
2020-05-27 |
Bobby R. Bruce | arch-riscv,misc: Added M5_VAR_USED to MiscRegNames |
tree | commitdiff |
2020-05-19 |
Gabe Black | arch,base,cpu,kern,sim: Encapsulate symbols in a class. |
tree | commitdiff |
2020-05-11 |
Ayaz Akram | arch-riscv,tests: small update to make gem5.fast compile |
tree | commitdiff |
2020-05-02 |
Nils Asmussen | arch-riscv: be prepared for CSR changes during PT walk. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: report that we don't have debugging support. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: respect IALIGN, influenced by toggling... |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: let FPU instructions fault if status.FS... |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: make uret,sret,mret SerializeAfter,NonSpecu... |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: make accesses to CSRs SerializeAfter. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: fault according to status.{TVM,TSK,TW}. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: added dummy implementation of wfi instruction. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: fault on mstatus accesses from lower privil... |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: ignore writes to SXL/UXL fields in status... |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: added (un)serialization of miscRegFile. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: show names of MiscRegs on accesses. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: fixed read of {M,S,U}TVEC. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: fixed formatting. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: implement RemoteGDB::acc for FS mode. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: implement sfence.vma to flush TLBs. |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: make sure only supported modes can be set... |
tree | commitdiff |
2020-04-29 |
Nils Asmussen | arch-riscv: added TLB and page table walker. |
tree | commitdiff |
2020-04-22 |
Gabe Black | base,arch,sim,cpu: Move object file loader components... |
tree | commitdiff |
2020-04-22 |
Gabe Black | configs,arch,sim: Move fixFuncEventAddr into the Worklo... |
tree | commitdiff |
2020-04-22 |
Gabe Black | arch,sim,kern,dev,cpu: Create a Workload SimObject. |
tree | commitdiff |
2020-03-27 |
Gabe Black | riscv: Fix RISCV builds by updating its use of pseudoIn... |
tree | commitdiff |
2020-03-26 |
Nils Asmussen | arch-riscv: print information about faults. |
tree | commitdiff |
2020-03-26 |
Nils Asmussen | arch-riscv: added support for pseudo instructions. |
tree | commitdiff |
2020-03-25 |
Matthew Poremba | sim-se: Switch to new MemState API |
tree | commitdiff |
2020-03-25 |
Matthew Poremba | sim-se: Extend MemState API to use VMAs |
tree | commitdiff |
2020-03-20 |
Gabe Black | arch,sim: Merge Process::syscall and Process::getDesc. |
tree | commitdiff |
2020-03-20 |
Gabe Black | arch,sim: Drop the syscall number from the syscall... |
tree | commitdiff |
2020-03-20 |
Gabe Black | arch,sim: Create a common structure to hold syscall... |
tree | commitdiff |
2020-03-19 |
Gabe Black | arch,cpu,mem,sim: Reimplement the SE translating proxy... |
tree | commitdiff |
2020-03-19 |
Gabe Black | arch: Eliminate vtophys and its switching header file. |
tree | commitdiff |
2020-03-19 |
Gabe Black | riscv: Implement translateFunctional. |
tree | commitdiff |
2020-03-17 |
Gabe Black | kern,arch: Refactor SkipFuncEvent to not use skipFunction. |
tree | commitdiff |
2020-03-12 |
Gabe Black | arch,sim: Get rid of the now unused setSyscallReturn... |
tree | commitdiff |
2020-03-12 |
Gabe Black | sim: Get rid of the now unused getSyscallArg method. |
tree | commitdiff |
2020-03-12 |
Gabe Black | riscv: Use a riscv specific GuestABI for riscv system... |
tree | commitdiff |
2020-03-12 |
Gabe Black | riscv: Convert RISCV specific syscalls to Guest ABI. |
tree | commitdiff |
2020-03-12 |
Gabe Black | arch,sim: Convert clone to GuestABI and define a cloneB... |
tree | commitdiff |
2020-03-11 |
Gabe Black | config,arch,cpu,kern,sim: Extract kernel information... |
tree | commitdiff |
2020-03-10 |
Giacomo Travaglini | misc: string.join has been removed in python3 |
tree | commitdiff |
2020-03-09 |
Gabe Black | arch,cpu: Get rid of unused/unimplemented vtophys variants. |
tree | commitdiff |
2020-03-04 |
Gabe Black | arch,cpu,mem: Replace the mmmapped IPR mechanism with... |
tree | commitdiff |
2020-02-26 |
Bobby R. Bruce | misc: merge branch 'release-staging-v19.0.0.0' into... |
tree | commitdiff |
2020-02-24 |
Bobby R. Bruce | misc: Merged release-staging-v19.0.0.0 into develop |
tree | commitdiff |
2020-02-19 |
Adrian Herrera | misc: pass ThreadContext on ISA clear |
tree | commitdiff |
2020-02-18 |
Gabe Black | riscv: Delete authors lists from riscv files. |
tree | commitdiff |
2020-02-11 |
Gabe Black | arch: Get rid of the generic mmapped IPR mechanism. |
tree | commitdiff |
2020-02-10 |
Gabe Black | riscv: Cast to float explicitly when comparing a float... |
tree | commitdiff |
2020-02-10 |
Gabe Black | arch: Add a bunch of missing override specifiers. |
tree | commitdiff |
2020-02-08 |
Gabe Black | arch,sim: Replace setuidFunc with ignoreFunc. |
tree | commitdiff |
2020-02-08 |
Gabe Black | arch: Switch SyscallDescABI in for SyscallDesc. |
tree | commitdiff |
2020-02-08 |
Gabe Black | arch: Simplify the SyscallDesc tables. |
tree | commitdiff |
2020-02-05 |
Gabe Black | arch: Introduce a base class for ISA classes. |
tree | commitdiff |
2020-02-01 |
Gabe Black | arch,sim: Merge initCPU into the ISA System classes. |
tree | commitdiff |
2020-02-01 |
Gabe Black | arch,sim: Merge initCPU and startupCPU. |
tree | commitdiff |
2019-12-10 |
Gabe Black | sim,arch: Collapse the ISA specific versions of m5Syscall. |
tree | commitdiff |
2019-12-10 |
Gabe Black | arch,cpu,sim: Push syscall number determination up... |
tree | commitdiff |
2019-12-10 |
Gabe Black | arch: Get rid of the now unused setSyscallArg. |
tree | commitdiff |
2019-12-10 |
Gabe Black | arch: Use ignoreWarnOnceFunc instead of the WarnOnce... |
tree | commitdiff |
2019-12-08 |
Alec Roelke | arch-riscv: set MaxMiscDestRegs to 2 |
tree | commitdiff |
2019-12-01 |
Ian Jiang | arch-riscv: Fix disassembling of immediate for c.lui... |
tree | commitdiff |
2019-11-26 |
Ian Jiang | arch-riscv: Fix immediate decoding for integer shift... |
tree | commitdiff |
2019-11-26 |
Ian Jiang | arch-riscv: Fix disassembling for fence and fence.i |
tree | commitdiff |
2019-11-25 |
Ian Jiang | arch-riscv: Fix disassembling for atomic instructions |
tree | commitdiff |
2019-11-25 |
Ian Jiang | arch-riscv: Fix disassembling of operand list for compr... |
tree | commitdiff |
2019-11-25 |
Ian Jiang | arch-riscv: Fix disassembling of immediate for U-type... |
tree | commitdiff |
2019-11-22 |
IanJiangICT | arch-riscv: Fix bug in serialize and unserialize of... |
tree | commitdiff |
2019-11-18 |
Gabe Black | arch: Get rid of the (Big|Little)EndianGuest namespaces. |
tree | commitdiff |
2019-11-18 |
Gabe Black | arch: Make and use endian specific versions of the... |
tree | commitdiff |
2019-11-02 |
Gabe Black | arch,cpu: Move endianness conversion of inst bytes... |
tree | commitdiff |
2019-10-30 |
Gabe Black | arch: Make endianness a property of the OS class syscal... |
tree | commitdiff |
2019-10-25 |
Gabe Black | mips,riscv: Get rid of some Alpha cruft in these System... |
tree | commitdiff |
2019-10-25 |
Gabe Black | cpu: Create a PCEventScope class to abstract the scope... |
tree | commitdiff |
2019-10-19 |
Gabe Black | arch: Make a base class for Interrupts. |
tree | commitdiff |
2019-10-16 |
Gabe Black | arch,base,sim: Move Process loader hooks into the Proce... |
tree | commitdiff |
2019-10-12 |
Gabe Black | arch,base: Separate the idea of a memory image and... |
tree | commitdiff |
2019-10-10 |
Gabe Black | arch,base: Stop loading the interpreter in ElfObject. |
tree | commitdiff |
2019-10-10 |
Gabe Black | arch, base: Stop assuming object files have three segments. |
tree | commitdiff |
2019-10-09 |
Gabe Black | arch-mips,arch-riscv,base: Get rid of the unused HexFil... |
tree | commitdiff |
2019-10-09 |
Gabe Black | base: Rename Section to Segment, and some of its members. |
tree | commitdiff |
2019-08-23 |
Alec Roelke | arch-riscv: fix GDB register cache |
tree | commitdiff |
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