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arch-arm: Add initial support for SVE contiguous loads/stores
[gem5.git]
/
src
/
arch
/
sparc
/
registers.hh
2019-02-01
Gabe Black
cpu, arch: Replace the CCReg type with RegVal.
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2019-01-30
Giacomo Gabrielli
arch,cpu: Add vector predicate registers
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2019-01-22
Gabe Black
sparc: Get rid of some register type definitions.
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2019-01-16
Gabe Black
arch: Make the ISA register types aliases for the globa...
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2018-11-05
Gabe Black
sparc: Switch the FloatReg and FloatRegBits types to...
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2018-10-17
Gabe Black
arch: Get rid of the unused type AnyReg.
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Added interface for vector reg file
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2017-07-05
Nathanael Premillieu
arch, cpu: Architectural Register structural indexing
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2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
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2015-07-26
Nilay Vaish
cpu: implements vector registers
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2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
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2013-10-15
Steve Reinhardt
cpu: rename *_DepTag constants to *_Reg_Base
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2013-10-15
Steve Reinhardt
isa: clean up register constants
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2012-06-05
Ali Saidi
O3: Clean up the O3 structures and try to pack them...
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2012-04-23
Gabe Black
ISA: Put parser generated files in a "generated" directory.
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2011-06-10
Korey Sewell
sparc: merge regr. updates w/last update
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2011-06-09
Korey Sewell
sparc: compilation fixes for inorder
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2010-11-11
Gabe Black
SPARC: Clean up some historical style issues.
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2010-08-26
Min Kyu Jeong
ARM: Fixed register flattening logic (FP_Base_DepTag...
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2009-07-13
Derek Hower
merge
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2009-07-09
Gabe Black
Registers: Add a registers.hh file as an ISA switched...
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