arch-arm: Add initial support for SVE contiguous loads/stores
[gem5.git] / src / arch / sparc / registers.hh
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal.
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-22 Gabe Blacksparc: Get rid of some register type definitions.
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa...
2018-11-05 Gabe Blacksparc: Switch the FloatReg and FloatRegBits types to...
2018-10-17 Gabe Blackarch: Get rid of the unused type AnyReg.
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2017-07-05 Nathanael Premillieuarch, cpu: Architectural Register structural indexing
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-10-15 Steve Reinhardtcpu: rename *_DepTag constants to *_Reg_Base
2013-10-15 Steve Reinhardtisa: clean up register constants
2012-06-05 Ali SaidiO3: Clean up the O3 structures and try to pack them...
2012-04-23 Gabe BlackISA: Put parser generated files in a "generated" directory.
2011-06-10 Korey Sewellsparc: merge regr. updates w/last update
2011-06-09 Korey Sewellsparc: compilation fixes for inorder
2010-11-11 Gabe BlackSPARC: Clean up some historical style issues.
2010-08-26 Min Kyu JeongARM: Fixed register flattening logic (FP_Base_DepTag...
2009-07-13 Derek Howermerge
2009-07-09 Gabe BlackRegisters: Add a registers.hh file as an ISA switched...