mem-cache: Add multiple eviction stats
[gem5.git] / src / arch / x86 / isa.hh
2019-01-31 Gabe Blackx86: Stop using/defining some ISA specific register...
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2017-07-05 Rekai Gonzalez-Alb... cpu: Simplify the rename interface and use RegId
2015-10-12 Andreas Hanssonmisc: Remove redundant compiler-specific defines
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout
2014-01-24 Andreas Hanssonarch: Make all register index flattening const
2014-01-24 Ali Saidiarch, cpu: Add support for flattening misc register...
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-02-19 Andreas Hanssonscons: Add warning for overloaded virtual functions
2013-01-13 Nilay Vaishx86: Changes to decoder, corrects 9376
2013-01-07 Andreas Sandbergarch: Move the ISA object to a separate section
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2013-01-05 Gabe BlackX86: Move address based decode caching in front of...
2011-04-15 Nathan Binkertincludes: sort all includes
2010-08-23 Gabe BlackX86: Create a directory for files that define register...
2009-07-18 Derek Howermerge
2009-07-18 Gabe BlackX86: Set up a named constant for the "fold bit" for...
2009-07-17 Gabe BlackX86: Shift some register flattening work into the decoder.
2009-07-13 Derek Howermerge
2009-07-10 Gabe BlackX86: Fold the MiscRegFile all the way into the ISA...
2009-07-09 Gabe BlackGet rid of the unused get(Data|Inst)Asid and (inst...
2009-07-09 Gabe BlackRegisters: Add an ISA object which replaces the MiscReg...