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mem-cache: Add multiple eviction stats
[gem5.git]
/
src
/
arch
/
x86
/
isa.hh
2019-01-31
Gabe Black
x86: Stop using/defining some ISA specific register...
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2019-01-30
Giacomo Gabrielli
arch,cpu: Add vector predicate registers
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Added interface for vector reg file
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Simplify the rename interface and use RegId
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2015-10-12
Andreas Hansson
misc: Remove redundant compiler-specific defines
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2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
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2015-07-26
Nilay Vaish
cpu: implements vector registers
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2015-07-07
Andreas Sandberg
sim: Refactor the serialization base class
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2015-02-16
Andreas Hansson
arch: Make readMiscRegNoEffect const throughout
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2014-01-24
Andreas Hansson
arch: Make all register index flattening const
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2014-01-24
Ali Saidi
arch, cpu: Add support for flattening misc register...
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2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
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2013-02-19
Andreas Hansson
scons: Add warning for overloaded virtual functions
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2013-01-13
Nilay Vaish
x86: Changes to decoder, corrects 9376
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2013-01-07
Andreas Sandberg
arch: Move the ISA object to a separate section
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2013-01-07
Andreas Sandberg
arch: Make the ISA class inherit from SimObject
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2013-01-05
Gabe Black
X86: Move address based decode caching in front of...
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2011-04-15
Nathan Binkert
includes: sort all includes
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2010-08-23
Gabe Black
X86: Create a directory for files that define register...
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2009-07-18
Derek Hower
merge
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2009-07-18
Gabe Black
X86: Set up a named constant for the "fold bit" for...
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2009-07-17
Gabe Black
X86: Shift some register flattening work into the decoder.
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2009-07-13
Derek Hower
merge
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2009-07-10
Gabe Black
X86: Fold the MiscRegFile all the way into the ISA...
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2009-07-09
Gabe Black
Get rid of the unused get(Data|Inst)Asid and (inst...
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2009-07-09
Gabe Black
Registers: Add an ISA object which replaces the MiscReg...
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