2019-04-11 |
Giacomo Travaglini | arch-arm: Enable PMSELR_EL0 read in PMU |
tree | commitdiff |
2019-04-03 |
Andrea Mondelli | misc: Removed inconsistency in O3* debug msgs |
tree | commitdiff |
2019-04-02 |
Giacomo Travaglini | dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt |
tree | commitdiff |
2019-04-01 |
Andrea Mondelli | dev-arm: Correct cast of template parameter |
tree | commitdiff |
2019-03-28 |
Javier Setoain | arch-arm: Fix use of bitwise operators on booleans |
tree | commitdiff |
2019-03-28 |
Giacomo Travaglini | arch-arm: Fix index generation for VecElem operands |
tree | commitdiff |
2019-03-25 |
Javier Setoain | arch-arm: Add missing fall-through defaults |
tree | commitdiff |
2019-03-25 |
Sandipan Das | arch-power: Rename program counter registers |
tree | commitdiff |
2019-03-25 |
Sandipan Das | arch-power: Simplify doubleword operand types |
tree | commitdiff |
2019-03-22 |
Tiago Muck | sim-se: Fixed initialization array size |
tree | commitdiff |
2019-03-21 |
Andrea Mondelli | dev-arm: ambiguous use of getPort() |
tree | commitdiff |
2019-03-19 |
Gabe Black | arch, cpu, dev, gpu, mem, sim, python: start using... |
tree | commitdiff |
2019-03-14 |
Giacomo Gabrielli | arch-arm,cpu: Add initial support for Arm SVE |
tree | commitdiff |
2019-03-11 |
Ryan Gambord | arch-hsail: changed gen.py shebang from python(3) to... |
tree | commitdiff |
2019-03-11 |
Ryan Gambord | arch-arm: Fixing implicit fallthrough build errors |
tree | commitdiff |
2019-03-01 |
Andrea Mondelli | mem-cache: alias to mem::getMasterPort in TLB class |
tree | commitdiff |
2019-03-01 |
Ciro Santilli | arch-arm: implement floating point aarch32 VCVTA family |
tree | commitdiff |
2019-02-23 |
Andreas Sandberg | python: Enforce absolute imports for Python 3 compatibility |
tree | commitdiff |
2019-02-20 |
Bagus Hanindhito | x86: Call the base class's regStats in X86ISA::TLB |
tree | commitdiff |
2019-02-18 |
Ivan Pizarro | arch-generic: Making base TLB class a MemObject |
tree | commitdiff |
2019-02-18 |
Giacomo Travaglini | arch-arm: Move GICv3 detection at startup time |
tree | commitdiff |
2019-02-13 |
Ayaz Akram | sim-se: update the arm kernel version |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Replace dict.has_key with 'key in dict' |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | python: Don't assume SimObjects live in the global... |
tree | commitdiff |
2019-02-12 |
Andreas Sandberg | arch-mips: Remove unused Python file |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: fix AMO, LR and SC instructions |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: fixed syscall return value |
tree | commitdiff |
2019-02-08 |
Tuan Ta | riscv: ignore nanosleep syscall |
tree | commitdiff |
2019-02-08 |
Tuan Ta | arch-riscv: initialize RISC-V's thread pointer register... |
tree | commitdiff |
2019-02-08 |
Giacomo Travaglini | arch-arm: Fix Virtual interrupts in AArch64 |
tree | commitdiff |
2019-02-08 |
Giacomo Travaglini | arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72... |
tree | commitdiff |
2019-02-08 |
Giacomo Travaglini | arch-arm: Allow ArmPPI usage for PMU |
tree | commitdiff |
2019-02-08 |
Ruben Ayrapetyan | arch-arm: Fix initialization of PMU counters |
tree | commitdiff |
2019-02-07 |
Austin Harris | arch-riscv: Enable support for riscv 32-bit in SE mode. |
tree | commitdiff |
2019-02-06 |
Tuan Ta | riscv: remove NonSpeculative flag from fence inst |
tree | commitdiff |
2019-02-06 |
Tuan Ta | arch-riscv: Initialize interrupt mask |
tree | commitdiff |
2019-02-05 |
Andrea Mondelli | misc: added missing override specifier |
tree | commitdiff |
2019-02-05 |
Austin Harris | riscv: Get rid of ISA specific register types in Interr... |
tree | commitdiff |
2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
tree | commitdiff |
2019-01-31 |
Gabe Black | power: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | null: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-31 |
Gabe Black | mips: Stop using architecture specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | alpha: Stop using architecture specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | x86: Stop using/defining some ISA specific register... |
tree | commitdiff |
2019-01-31 |
Gabe Black | riscv: Get rid of some ISA specific register types. |
tree | commitdiff |
2019-01-31 |
Gabe Black | arch: cpu: Rename *FloatRegBits* to *FloatReg*. |
tree | commitdiff |
2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
tree | commitdiff |
2019-01-30 |
Giacomo Travaglini | arch-arm, configs: Create single instance of DTB autoge... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove floatReg operand type |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Use VecElem instead of FloatReg for FP instru... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch: Fix VecElem Operand generation in ISA parser |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | cpu, arch, arch-arm: Wire unused VecElem code in the... |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Inital vector rename mode depending on A32/A64 |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch-arm: Remove unused float operands |
tree | commitdiff |
2019-01-25 |
Giacomo Travaglini | arch: Provide traceback when parsing ISA code |
tree | commitdiff |
2019-01-24 |
Gabe Black | hsail: Remove the MiscReg type. |
tree | commitdiff |
2019-01-24 |
Gabe Black | base: arch: Get rid of the now unused FloatRegVal type. |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: IsStoreConditional flag set depending on... |
tree | commitdiff |
2019-01-23 |
Giacomo Travaglini | arch-arm: Remove SWP and SWPB instructions |
tree | commitdiff |
2019-01-23 |
Gabe Black | arm: Replace MiscReg with RegVal in utility.(hh|cc). |
tree | commitdiff |
2019-01-22 |
Gabe Black | sparc: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
tree | commitdiff |
2019-01-22 |
Gabe Black | arm: Get rid of some register type definitions. |
tree | commitdiff |
2019-01-22 |
Ciro Santilli | arch-arm: implement the GDB XML target description... |
tree | commitdiff |
2019-01-22 |
Giacomo Travaglini | arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se add readv and modifies writev |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add ability to get/set sock metadata |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add syscalls related to polling |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add calls for network transmissions |
tree | commitdiff |
2019-01-22 |
Brandon Potter | sim-se: add socket-based functionality |
tree | commitdiff |
2019-01-16 |
Gabe Black | cpu: dev: sim: gpu-compute: Banish some ISA specific... |
tree | commitdiff |
2019-01-16 |
Gabe Black | arch: Make the ISA register types aliases for the globa... |
tree | commitdiff |
2019-01-16 |
Gabe Black | arm: Make the fp register types 64 bits. |
tree | commitdiff |
2019-01-16 |
Giacomo Travaglini | arch-arm: Read VMPIDR instead of MPIDR when EL2 is... |
tree | commitdiff |
2019-01-16 |
Anouk Van Laer | arch-arm: Added TLBI_ALL EL2 instruction |
tree | commitdiff |
2019-01-16 |
Alec Roelke | arch-riscv: Add interrupt handling |
tree | commitdiff |
2019-01-16 |
Alec Roelke | arch-riscv: Fix reset function and style |
tree | commitdiff |
2019-01-15 |
Giacomo Travaglini | arch-arm: Fix usage of RegId constructor for VecElem |
tree | commitdiff |
2019-01-14 |
Gabe Black | arm: Stop using the FloatReg and FloatRegBits types. |
tree | commitdiff |
2019-01-10 |
Javier Setoain | sim-se, arch-arm: Add support for getdents64 |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | arch-arm, sim-se: Add support for TLS in clone |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | arch-arm, sim-se: Fix incorrect SP handling in clone |
tree | commitdiff |
2019-01-10 |
Andreas Sandberg | sim-se: Refactor clone to avoid most ifdefs |
tree | commitdiff |
2019-01-10 |
Javier Setoain | arch-arm, sim-se: Wire up syscalls needed for pthreads |
tree | commitdiff |
2019-01-10 |
Jairo Balart | dev-arm: Add a GICv3 model |
tree | commitdiff |
2019-01-09 |
Ivan Pizarro | arch-arm: Additional bits in misc ARM registers to... |
tree | commitdiff |
2019-01-03 |
Curtis Dunham | arm: properly handle RES0/1 for SCTLRs |
tree | commitdiff |
2018-12-20 |
Gabe Black | arch, cpu: Remove float type accessors. |
tree | commitdiff |
2018-12-19 |
Giacomo Travaglini | arch-arm: Add Crypto in SE mode |
tree | commitdiff |
2018-12-18 |
Gabe Black | arch: Make the ISA parser always use binary floating... |
tree | commitdiff |
2018-12-05 |
Tony Gutierrez | arch-x86: Add sys/syscall.h to x86 process.cc/syscall_e... |
tree | commitdiff |
2018-12-03 |
Ciro Santilli | arch-arm: correctly set floats from GDB on aarch64 |
tree | commitdiff |
2018-12-03 |
Ciro Santilli | arch-arm: only change the pc address when GDB registers... |
tree | commitdiff |
2018-12-03 |
Ciro Santilli | arch-arm: fix the aarch64 GDB stub |
tree | commitdiff |
2018-11-28 |
Nikos Nikoleris | arch-arm: Add missing template declaration |
tree | commitdiff |
2018-11-28 |
Rekai Gonzalez-Alb... | cpu,arch-arm: Initialise data members |
tree | commitdiff |
2018-11-28 |
Matteo Andreozzi | arch-arm: clang compilation fixes |
tree | commitdiff |
2018-11-27 |
Gabe Black | hsail: Fix a warning/build failure for HSAIL_X86. |
tree | commitdiff |
2018-11-27 |
Gabe Black | arch, base, cpu, gpu, mem: Replace assert(0 or false... |
tree | commitdiff |
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