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cpu: Get rid of the (read|set)RegOtherThread methods.
[gem5.git] / src / arch /
2019-04-29 Gabe Blackmips: Implement readRegOtherThread and setRegOtherThrea... tree | commitdiff
2019-04-29 Giacomo Travagliniarch-arm: Faults DebugFlag now printing inst opcode... tree | commitdiff
2019-04-29 Giacomo Travagliniarch-arm: Report real instruction encoding when Undefined tree | commitdiff
2019-04-28 Gabe Blackarch, sim: Simplify the AuxVector type. tree | commitdiff
2019-04-28 Gabe Blackmem: Remove the ISA specialized versions of port proxy... tree | commitdiff
2019-04-28 Gabe Blackmem: Minimize the use of MemObject. tree | commitdiff
2019-04-26 Giacomo Travagliniarch-arm: updateMiscReg not setting isHyp in aarch64 tree | commitdiff
2019-04-26 Gabe Blackarm: Factor some repetition out of the ProcessInfo... tree | commitdiff
2019-04-25 Gabe Blackarm: Fix some style issues in stacktrace.cc. tree | commitdiff
2019-04-25 Gabe Blackx86: Refactor the ProcessInfo constructor. tree | commitdiff
2019-04-25 Gabe Blackx86: Fix some style issues in stacktrace.cc. tree | commitdiff
2019-04-25 Giacomo Travagliniarch-arm: Remove un-needed hyp flag in TLBI operations tree | commitdiff
2019-04-25 Giacomo Travagliniarch-arm: Correct target EL field in TLBI operations tree | commitdiff
2019-04-22 Alexandru Dutusim-se: Enhance clone for X86KvmCPU tree | commitdiff
2019-04-22 Gabe Blackcpu: Eliminate the ProxyThreadContext class. tree | commitdiff
2019-04-11 Giacomo Travagliniarch-arm: Enable PMSELR_EL0 read in PMU tree | commitdiff
2019-04-03 Andrea Mondellimisc: Removed inconsistency in O3* debug msgs tree | commitdiff
2019-04-02 Giacomo Travaglinidev-arm: Make GICv3 maintenance interrupt an ArmInterrupt tree | commitdiff
2019-04-01 Andrea Mondellidev-arm: Correct cast of template parameter tree | commitdiff
2019-03-28 Javier Setoainarch-arm: Fix use of bitwise operators on booleans tree | commitdiff
2019-03-28 Giacomo Travagliniarch-arm: Fix index generation for VecElem operands tree | commitdiff
2019-03-25 Javier Setoainarch-arm: Add missing fall-through defaults tree | commitdiff
2019-03-25 Sandipan Dasarch-power: Rename program counter registers tree | commitdiff
2019-03-25 Sandipan Dasarch-power: Simplify doubleword operand types tree | commitdiff
2019-03-22 Tiago Mucksim-se: Fixed initialization array size tree | commitdiff
2019-03-21 Andrea Mondellidev-arm: ambiguous use of getPort() tree | commitdiff
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using... tree | commitdiff
2019-03-14 Giacomo Gabrielliarch-arm,cpu: Add initial support for Arm SVE tree | commitdiff
2019-03-11 Ryan Gambordarch-hsail: changed gen.py shebang from python(3) to... tree | commitdiff
2019-03-11 Ryan Gambordarch-arm: Fixing implicit fallthrough build errors tree | commitdiff
2019-03-01 Andrea Mondellimem-cache: alias to mem::getMasterPort in TLB class tree | commitdiff
2019-03-01 Ciro Santilliarch-arm: implement floating point aarch32 VCVTA family tree | commitdiff
2019-02-23 Andreas Sandbergpython: Enforce absolute imports for Python 3 compatibility tree | commitdiff
2019-02-20 Bagus Hanindhitox86: Call the base class's regStats in X86ISA::TLB tree | commitdiff
2019-02-18 Ivan Pizarroarch-generic: Making base TLB class a MemObject tree | commitdiff
2019-02-18 Giacomo Travagliniarch-arm: Move GICv3 detection at startup time tree | commitdiff
2019-02-13 Ayaz Akramsim-se: update the arm kernel version tree | commitdiff
2019-02-12 Andreas Sandbergpython: Replace dict.has_key with 'key in dict' tree | commitdiff
2019-02-12 Andreas Sandbergpython: Don't assume SimObjects live in the global... tree | commitdiff
2019-02-12 Andreas Sandbergarch-mips: Remove unused Python file tree | commitdiff
2019-02-08 Tuan Tariscv: fix AMO, LR and SC instructions tree | commitdiff
2019-02-08 Tuan Tariscv: fixed syscall return value tree | commitdiff
2019-02-08 Tuan Tariscv: ignore nanosleep syscall tree | commitdiff
2019-02-08 Tuan Taarch-riscv: initialize RISC-V's thread pointer register... tree | commitdiff
2019-02-08 Giacomo Travagliniarch-arm: Fix Virtual interrupts in AArch64 tree | commitdiff
2019-02-08 Giacomo Travagliniarch-arm: Fix extra comma in b7ce897f1e9545785bde982f72... tree | commitdiff
2019-02-08 Giacomo Travagliniarch-arm: Allow ArmPPI usage for PMU tree | commitdiff
2019-02-08 Ruben Ayrapetyanarch-arm: Fix initialization of PMU counters tree | commitdiff
2019-02-07 Austin Harrisarch-riscv: Enable support for riscv 32-bit in SE mode. tree | commitdiff
2019-02-06 Tuan Tariscv: remove NonSpeculative flag from fence inst tree | commitdiff
2019-02-06 Tuan Taarch-riscv: Initialize interrupt mask tree | commitdiff
2019-02-05 Andrea Mondellimisc: added missing override specifier tree | commitdiff
2019-02-05 Austin Harrisriscv: Get rid of ISA specific register types in Interr... tree | commitdiff
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal. tree | commitdiff
2019-01-31 Gabe Blackpower: Get rid of some ISA specific register types. tree | commitdiff
2019-01-31 Gabe Blacknull: Get rid of some register type definitions. tree | commitdiff
2019-01-31 Gabe Blackmips: Stop using architecture specific register types. tree | commitdiff
2019-01-31 Gabe Blackalpha: Stop using architecture specific register types. tree | commitdiff
2019-01-31 Gabe Blackx86: Stop using/defining some ISA specific register... tree | commitdiff
2019-01-31 Gabe Blackriscv: Get rid of some ISA specific register types. tree | commitdiff
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*. tree | commitdiff
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers tree | commitdiff
2019-01-30 Giacomo Travagliniarch-arm, configs: Create single instance of DTB autoge... tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Remove floatReg operand type tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Use VecElem instead of FloatReg for FP instru... tree | commitdiff
2019-01-25 Giacomo Travagliniarch: Fix VecElem Operand generation in ISA parser tree | commitdiff
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the... tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Inital vector rename mode depending on A32/A64 tree | commitdiff
2019-01-25 Giacomo Travagliniarch-arm: Remove unused float operands tree | commitdiff
2019-01-25 Giacomo Travagliniarch: Provide traceback when parsing ISA code tree | commitdiff
2019-01-24 Gabe Blackhsail: Remove the MiscReg type. tree | commitdiff
2019-01-24 Gabe Blackbase: arch: Get rid of the now unused FloatRegVal type. tree | commitdiff
2019-01-23 Giacomo Travagliniarch-arm: Implement LoadAcquire/StoreRelease in AArch32 tree | commitdiff
2019-01-23 Giacomo Travagliniarch-arm: IsStoreConditional flag set depending on... tree | commitdiff
2019-01-23 Giacomo Travagliniarch-arm: Remove SWP and SWPB instructions tree | commitdiff
2019-01-23 Gabe Blackarm: Replace MiscReg with RegVal in utility.(hh|cc). tree | commitdiff
2019-01-22 Gabe Blacksparc: Get rid of some register type definitions. tree | commitdiff
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference. tree | commitdiff
2019-01-22 Gabe Blackarm: Get rid of some register type definitions. tree | commitdiff
2019-01-22 Ciro Santilliarch-arm: implement the GDB XML target description... tree | commitdiff
2019-01-22 Giacomo Travagliniarch-arm: Move AArch32 IMPLEMENTATION DEFINED registers tree | commitdiff
2019-01-22 Brandon Pottersim-se add readv and modifies writev tree | commitdiff
2019-01-22 Brandon Pottersim-se: add ability to get/set sock metadata tree | commitdiff
2019-01-22 Brandon Pottersim-se: add syscalls related to polling tree | commitdiff
2019-01-22 Brandon Pottersim-se: add calls for network transmissions tree | commitdiff
2019-01-22 Brandon Pottersim-se: add socket-based functionality tree | commitdiff
2019-01-16 Gabe Blackcpu: dev: sim: gpu-compute: Banish some ISA specific... tree | commitdiff
2019-01-16 Gabe Blackarch: Make the ISA register types aliases for the globa... tree | commitdiff
2019-01-16 Gabe Blackarm: Make the fp register types 64 bits. tree | commitdiff
2019-01-16 Giacomo Travagliniarch-arm: Read VMPIDR instead of MPIDR when EL2 is... tree | commitdiff
2019-01-16 Anouk Van Laerarch-arm: Added TLBI_ALL EL2 instruction tree | commitdiff
2019-01-16 Alec Roelkearch-riscv: Add interrupt handling tree | commitdiff
2019-01-16 Alec Roelkearch-riscv: Fix reset function and style tree | commitdiff
2019-01-15 Giacomo Travagliniarch-arm: Fix usage of RegId constructor for VecElem tree | commitdiff
2019-01-14 Gabe Blackarm: Stop using the FloatReg and FloatRegBits types. tree | commitdiff
2019-01-10 Javier Setoainsim-se, arch-arm: Add support for getdents64 tree | commitdiff
2019-01-10 Andreas Sandbergarch-arm, sim-se: Add support for TLS in clone tree | commitdiff
2019-01-10 Andreas Sandbergarch-arm, sim-se: Fix incorrect SP handling in clone tree | commitdiff
2019-01-10 Andreas Sandbergsim-se: Refactor clone to avoid most ifdefs tree | commitdiff
2019-01-10 Javier Setoainarch-arm, sim-se: Wire up syscalls needed for pthreads tree | commitdiff
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