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kvm, arm: Refactor KVM GIC device
[gem5.git]
/
src
/
cpu
/
BaseCPU.py
2016-04-05
Geoffrey Blake
cpu: Query CPU for inst executed from Python
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2015-09-30
Mitch Hayenga
isa,cpu: Add support for FS SMT Interrupts
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2015-03-02
Andreas Hansson
mem: Move crossbar default latencies to subclasses
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2015-03-02
Andreas Hansson
arm: Share a port for the two table walker objects
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2015-01-25
Ali Saidi
cpu: Put all CPU instruction tracers in a single file
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2014-09-20
Andreas Hansson
mem: Rename Bus to XBar to better reflect its behaviour
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2014-05-09
Akash Bagdia
cpu, arm: Allow the specification of a socket field
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2014-01-24
ARM gem5 Developers
arm: Add support for ARMv8 (AArch64 & AArch32)
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2013-09-04
Andreas Hansson
cpu: Move the branch predictor out of the BaseCPU
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2013-06-27
Akash Bagdia
sim: Add the notion of clock domains to all ClockedObjects
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2013-06-27
Akash Bagdia
config: Remove redundant explicit setting of default...
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2013-06-11
Andreas Sandberg
cpu: Add support for scheduling multiple inst/load...
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2013-04-22
Timothy M. Jones
cpu: Let python scripts obtain the number of instructio...
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2013-04-22
Dam Sunwoo
cpu: generate SimPoint basic block vector profiles
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2013-02-19
Andreas Hansson
x86: Move APIC clock divider to Python
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2013-02-15
Andreas Sandberg
cpu: Add CPU metadata om the Python classes
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2013-01-24
Nilay Vaish ext...
branch predictor: move out of o3 and inorder cpus
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2013-01-07
Andreas Sandberg
cpu: Flush TLBs on switchOut()
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2013-01-07
Andreas Sandberg
cpu: Rename defer_registration->switched_out
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2013-01-07
Andreas Sandberg
cpu: Introduce sanity checks when switching between...
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2013-01-07
Andreas Sandberg
arch: Make the ISA class inherit from SimObject
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2012-11-02
Andreas Sandberg
sim: Include object header files in SWIG interfaces
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2012-10-15
Andreas Hansson
Regression: Use CPU clock and 32-byte width for L1...
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2012-09-25
Andreas Sandberg
sim: Move CPU-specific methods from SimObject to the...
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2012-08-28
Andreas Hansson
Clock: Add a Cycles wrapper class and use where applicable
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2012-08-21
Andreas Hansson
CPU: Remove overloaded function_trace_start parameter
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2012-08-21
Andreas Hansson
Clock: Move the clock and related functions to ClockedO...
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2012-05-31
Andreas Hansson
Bus: Split the bus into a non-coherent and coherent bus
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2012-03-09
Geoffrey Blake
CheckerCPU: Make CheckerCPU runtime selectable instead...
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2012-03-01
Nilay Vaish
x86: Fix switching of CPUs
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2012-02-13
Andreas Hansson
MEM: Introduce the master/slave port roles in the Pytho...
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Geoffrey Blake
CheckerCPU: Re-factor CheckerCPU to be compatible with...
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2012-01-31
Gabe Black
Merge with main repository.
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2012-01-29
Gabe Black
Yet another merge with the main repository.
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-16
Gabe Black
Merge yet again with the main repository.
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2012-01-17
Andreas Hansson
CPU: Moving towards a more general port across CPU...
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2012-01-07
Gabe Black
Another merge with the main repository.
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2012-01-07
Gabe Black
Merge with the main repository again.
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2012-01-07
Gabe Black
Merge with main repository.
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2011-12-01
Ali Saidi
ARM: Add support for having a TLB cache.
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2011-11-18
Gabe Black
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
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2011-11-02
Gabe Black
SE/FS: Get rid of FULL_SYSTEM in sim.
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2011-10-16
Gabe Black
ARM: Turn on the page table walker on ARM in SE mode.
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2011-10-13
Gabe Black
X86: Turn on the page table walker in SE mode.
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2011-10-09
Gabe Black
SE/FS: Build the Interrupt objects in SE mode.
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2011-03-26
Korey Sewell
mips: cleanup ISA-specific code
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2011-02-07
Joel Hestness
mcpat: Adds McPAT performance counters
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2011-02-04
Gabe Black
Config: Keep track of uncached and cached ports separately.
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2011-02-02
Gabe Black
X86: Add L1 caches for the TLB walkers.
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2010-11-23
Gabe Black
X86: Loosen an assert for x86 and connect the APIC...
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2010-06-02
Ali Saidi
ARM: Implement the ARM TLB/Tablewalker. Needs performan...
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2010-01-19
Derek Hower
merge
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2009-10-27
Timothy M. Jones
POWER: Add support for the Power ISA
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2009-09-22
Nathan Binkert
python: Move more code into m5.util allow SCons to...
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2009-04-21
Nathan Binkert
Automated merge with ssh://m5sim.org//repo/m5
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2009-04-21
Nathan Binkert
arm: Unify the ARM tlb. We forgot about this when...
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2009-04-09
Nathan Binkert
tlb: More fixing of unified TLB
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2009-04-09
Gabe Black
tlb: Don't separate the TLB classes into an instruction...
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2009-04-06
Gabe Black
Merge ARM into the head. ARM will compile but may not...
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2009-01-31
Ali Saidi
Config: Cause a fatal() when a parameter without a...
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2008-12-17
Steve Reinhardt
Make Alpha pseudo-insts available from SE mode.
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2008-11-03
Lisa Hsu
make BaseCPU the provider of _cpuId, and cpuId() instea...
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2008-10-12
Gabe Black
X86: Fix the ordering of special physical address ranges.
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2008-10-12
Gabe Black
X86: Make APICs communicate through the memory system.
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2008-10-12
Gabe Black
X86: Make the local APIC accessible through the memory...
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2008-10-12
Gabe Black
Turn Interrupts objects into SimObjects. Also, move...
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2008-08-11
Nathan Binkert
params: Convert the CPU objects to use the auto generat...
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2008-02-11
Steve Reinhardt
Automated merge with file:/home/stever/hg/m5-orig
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2008-02-06
Stephen Hines
Add base ARM code to M5
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2007-11-21
Gabe Black
imported patch pagewalker.patch
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2007-11-15
Korey Sewell
merge Ali's config change...
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2007-11-15
Korey Sewell
branch merge
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2007-11-13
Korey Sewell
Add in files from merge-bare-iron, get them compiling...
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2007-11-13
Gabe Black
X86: Separate out the page table walker into it's own...
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2007-11-12
Gabe Black
X86: Work on the page table walker, TLB, and related...
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2007-11-12
Gabe Black
X86: Implement a page table walker.
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2007-08-28
Gabe Black
Merge with head.
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2007-08-27
Gabe Black
Address Translation: Make SE mode use an actual TLB...
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2007-08-14
Ali Saidi
Merge IGNORE_STYLE change and my change.
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2007-08-12
Nathan Binkert
merge
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2007-08-08
Vincentius Robby
Added fastmem option.
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2007-07-29
Steve Reinhardt
Merge Gabe's changes from head.
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2007-07-29
Gabe Black
Merge ... head. style.py was also missing an argument...
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2007-07-29
Gabe Black
Merge with head.
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2007-07-29
Gabe Black
Turn the instruction tracing code into pluggable sim...
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2007-06-20
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-05-31
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-05-28
Steve Reinhardt
Merge vm1.(none):/home/stever/bk/newmem-head
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2007-05-28
Nathan Binkert
Move SimObject python files alongside the C++ and fix
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