o3 cpu: remove some unused buggy functions in the lsq
[gem5.git] / src / cpu / BaseCPU.py
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-10-15 Andreas HanssonRegression: Use CPU clock and 32-byte width for L1...
2012-09-25 Andreas Sandbergsim: Move CPU-specific methods from SimObject to the...
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-21 Andreas HanssonCPU: Remove overloaded function_trace_start parameter
2012-08-21 Andreas HanssonClock: Move the clock and related functions to ClockedO...
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-01 Nilay Vaishx86: Fix switching of CPUs
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonCPU: Moving towards a more general port across CPU...
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-12-01 Ali SaidiARM: Add support for having a TLB cache.
2011-11-18 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-11-02 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in sim.
2011-10-16 Gabe BlackARM: Turn on the page table walker on ARM in SE mode.
2011-10-13 Gabe BlackX86: Turn on the page table walker in SE mode.
2011-10-09 Gabe BlackSE/FS: Build the Interrupt objects in SE mode.
2011-03-26 Korey Sewellmips: cleanup ISA-specific code
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately.
2011-02-02 Gabe BlackX86: Add L1 caches for the TLB walkers.
2010-11-23 Gabe BlackX86: Loosen an assert for x86 and connect the APIC...
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan...
2010-01-19 Derek Howermerge
2009-10-27 Timothy M. JonesPOWER: Add support for the Power ISA
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to...
2009-04-21 Nathan BinkertAutomated merge with ssh://m5sim.org//repo/m5
2009-04-21 Nathan Binkertarm: Unify the ARM tlb. We forgot about this when...
2009-04-09 Nathan Binkerttlb: More fixing of unified TLB
2009-04-09 Gabe Blacktlb: Don't separate the TLB classes into an instruction...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-01-31 Ali SaidiConfig: Cause a fatal() when a parameter without a...
2008-12-17 Steve ReinhardtMake Alpha pseudo-insts available from SE mode.
2008-11-03 Lisa Hsumake BaseCPU the provider of _cpuId, and cpuId() instea...
2008-10-12 Gabe BlackX86: Fix the ordering of special physical address ranges.
2008-10-12 Gabe BlackX86: Make APICs communicate through the memory system.
2008-10-12 Gabe BlackX86: Make the local APIC accessible through the memory...
2008-10-12 Gabe BlackTurn Interrupts objects into SimObjects. Also, move...
2008-08-11 Nathan Binkertparams: Convert the CPU objects to use the auto generat...
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-06 Stephen HinesAdd base ARM code to M5
2007-11-21 Gabe Blackimported patch pagewalker.patch
2007-11-15 Korey Sewellmerge Ali's config change...
2007-11-15 Korey Sewellbranch merge
2007-11-13 Korey SewellAdd in files from merge-bare-iron, get them compiling...
2007-11-13 Gabe BlackX86: Separate out the page table walker into it's own...
2007-11-12 Gabe BlackX86: Work on the page table walker, TLB, and related...
2007-11-12 Gabe BlackX86: Implement a page table walker.
2007-08-28 Gabe BlackMerge with head.
2007-08-27 Gabe BlackAddress Translation: Make SE mode use an actual TLB...
2007-08-14 Ali SaidiMerge IGNORE_STYLE change and my change.
2007-08-12 Nathan Binkertmerge
2007-08-08 Vincentius RobbyAdded fastmem option.
2007-07-29 Steve ReinhardtMerge Gabe's changes from head.
2007-07-29 Gabe BlackMerge ... head. style.py was also missing an argument...
2007-07-29 Gabe BlackMerge with head.
2007-07-29 Gabe BlackTurn the instruction tracing code into pluggable sim...
2007-06-20 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-31 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-28 Steve ReinhardtMerge vm1.(none):/home/stever/bk/newmem-head
2007-05-28 Nathan BinkertMove SimObject python files alongside the C++ and fix