git.libre-soc.org Git - gem5.git/history - src/cpu/StaticInstFlags.py

2020-09-15	Gabe Black	mips,cpu: Get rid of the IsERET StaticInst flag.	blob \| commitdiff \| raw
2020-09-15	Gabe Black	cpu: Get rid of the IsThreadSync StaticInst flag.	blob \| commitdiff \| raw \| diff to current
2020-09-15	Gabe Black	mips,cpu: Get rid of the IsCondDelaySlot StaticInst...	blob \| commitdiff \| raw \| diff to current
2020-09-07	Timothy Hayes	cpu: Add HTM Instruction Flags	blob \| commitdiff \| raw \| diff to current
2020-02-26	Bobby R. Bruce	misc: merge branch 'release-staging-v19.0.0.0' into...	blob \| commitdiff \| raw \| diff to current
2020-02-24	Bobby R. Bruce	misc: Merged release-staging-v19.0.0.0 into develop	blob \| commitdiff \| raw \| diff to current
2020-02-17	Gabe Black	cpu: Delete authors lists from the cpu directory.	blob \| commitdiff \| raw \| diff to current
2018-06-14	Tuan Ta	cpu: add a new instruction type 'Atomic'	blob \| commitdiff \| raw \| diff to current
2017-07-05	Rekai Gonzalez-Alb...	arch: ISA parser additions of vector registers	blob \| commitdiff \| raw \| diff to current
2015-07-28	Nilay Vaish	revert 5af8f40d8f2c	blob \| commitdiff \| raw \| diff to current
2015-07-26	Nilay Vaish	cpu: implements vector registers	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andrew Bardsley	cpu: Add flag name printing to StaticInst	blob \| commitdiff \| raw \| diff to current