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X86: Recognize and handle the lock legacy prefix.
[gem5.git]
/
src
/
cpu
/
base.hh
2009-04-06
Gabe Black
Merge ARM into the head. ARM will compile but may not...
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2009-03-06
Nathan Binkert
stats: Fix all stats usages to deal with template fixes
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2009-01-24
Nathan Binkert
cpu: provide a wakeup mechanism that can be used to...
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2008-11-04
Lisa Hsu
get rid of all instances of readTid() and getThreadNum...
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2008-11-03
Lisa Hsu
make BaseCPU the provider of _cpuId, and cpuId() instea...
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2008-10-21
Nathan Binkert
style: Use the correct m5 style for things relating...
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2008-10-12
Gabe Black
CPU: Create a microcode ROM object in the CPU which...
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2008-10-12
Gabe Black
Turn Interrupts objects into SimObjects. Also, move...
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2008-10-12
Gabe Black
CPU: Eliminate the get_vec function.
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2008-10-11
Gabe Black
CPU: Add a getInterruptController function
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2008-10-09
Nathan Binkert
eventq: convert all usage of events to use the new...
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2008-08-18
Richard Strong
Changed BaseCPU::ProfileEvent's interval member to...
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2008-08-11
Nathan Binkert
params: Convert the CPU objects to use the auto generat...
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2008-02-11
Steve Reinhardt
Automated merge with file:/home/stever/hg/m5-orig
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2008-02-06
Stephen Hines
Make the Event::description() a const function
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2007-11-15
Korey Sewell
merge Ali's config change...
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2007-11-15
Korey Sewell
add core specific parameter to BaseCPU params
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2007-11-15
Korey Sewell
branch merge
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2007-11-13
Korey Sewell
Add in files from merge-bare-iron, get them compiling...
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2007-10-31
Steve Reinhardt
Merge in bus DPRINTF changes.
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2007-10-03
Gabe Black
Merge with head.
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2007-09-28
Ali Saidi
Rename cycles() function to ticks()
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2007-09-28
Ali Saidi
Update statistics to use cycles properly instead of...
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2007-07-29
Steve Reinhardt
Merge Gabe's changes from head.
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2007-07-29
Gabe Black
Merge ... head. style.py was also missing an argument...
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2007-07-29
Gabe Black
Merge with head.
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2007-07-29
Gabe Black
Turn the instruction tracing code into pluggable sim...
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2007-04-03
Ali Saidi
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
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2007-03-27
Ron Dreslinski
Merge zizzer:/bk/newmem
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2007-03-23
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2007-03-16
Ali Saidi
Merge zizzer:/bk/newmem
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2007-03-15
Ali Saidi
Merge zizzer:/bk/newmem
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2007-03-15
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-15
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-15
Gabe Black
Make the predecoder an object with it's own switched...
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2007-03-09
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-09
Ali Saidi
Merge zizzer:/bk/newmem
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2007-03-09
Kevin Lim
Two fixes:
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2007-03-06
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-05
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-03-04
Ali Saidi
Merge zizzer:/bk/newmem
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2007-03-03
Ali Saidi
Implement Niagara I/O interface and rework interrupts
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2007-02-01
Lisa Hsu
Merge zizzer:/bk/newmem
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2007-01-30
Ali Saidi
Merge zizzer:/bk/newmem
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2007-01-30
Ali Saidi
Make SPARC checkpointing work
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2007-01-27
Gabe Black
Merge zizzer:/bk/newmem
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2007-01-26
Ali Saidi
Merge zizzer:/bk/newmem
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2007-01-26
Ali Saidi
Merge zizzer:/bk/newmem
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2007-01-26
Ali Saidi
Merge zeep.pool:/z/saidi/work/m5.newmem
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2007-01-26
Lisa Hsu
Merge zizzer:/bk/newmem
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2007-01-26
Lisa Hsu
eliminate cpu checkInterrupts bool, it is redundant...
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2007-01-23
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-01-22
Ali Saidi
Merge zizzer:/bk/newmem
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2007-01-20
Lisa Hsu
Merge zed.eecs.umich.edu:/.automount/zeep/z/saidi/work...
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2007-01-11
Lisa Hsu
Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
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2007-01-08
Lisa Hsu
the way i understand it, interrupts in m5 is a little...
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2006-12-16
Gabe Black
Merge zizzer:/bk/newmem
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2006-12-15
Lisa Hsu
Merge zizzer:/bk/newmem
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2006-12-15
Lisa Hsu
Merge zizzer:/bk/sparcfs
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2006-12-13
Lisa Hsu
Merge zizzer:/bk/newmem
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2006-12-13
Lisa Hsu
Merge zizzer:/bk/newmem
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2006-12-13
Lisa Hsu
Merge zizzer:/bk/newmem
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2006-12-05
Gabe Black
Merge zizzer:/bk/sparcfs
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2006-12-04
Lisa Hsu
Merge zizzer:/bk/sparcfs
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2006-12-04
Ali Saidi
More changes to get SPARC fs closer. Now at 1.2M cycles...
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2006-11-23
Ali Saidi
Merge zizzer:/bk/sparcfs
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2006-11-16
Gabe Black
Merge zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
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2006-11-16
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem/
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2006-11-14
Ron Dreslinski
Merge zizzer:/bk/newmem
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2006-11-14
Ron Dreslinski
Merge zizzer:/bk/newmem
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2006-11-14
Ron Dreslinski
Make cpu's capable of having a phase shift
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2006-11-13
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem/
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2006-11-13
Kevin Lim
Merge ktlim@zamp:./local/clean/tmp/test-regress
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2006-11-12
Ron Dreslinski
Merge zizzer:/bk/newmem
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2006-11-12
Nathan Binkert
Get rid of the ParamContext for pseudo instructions...
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2006-11-10
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-11-09
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-11-08
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem/
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2006-11-08
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem/
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2006-11-08
Gabe Black
Merge zeep.eecs.umich.edu:/home/gblack/m5/newmem
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2006-11-07
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem/
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2006-11-06
Ali Saidi
Merge zizzer:/bk/newmem
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2006-11-06
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-11-06
Kevin Lim
Clean up clock phase drift code a bit.
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2006-11-03
Gabe Black
Got rid of "inPalMode". Some places are still effective...
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2006-11-03
Gabe Black
Add a new file which describes an ISA's interrupt handl...
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2006-10-12
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2006-10-10
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-10-08
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2006-10-08
Ron Dreslinski
Merge zizzer:/z/m5/Bitkeeper/newmem
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2006-10-08
Steve Reinhardt
Implement Alpha LL/SC support for SimpleCPU (Atomic...
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2006-10-07
Ali Saidi
Merge zizzer:/bk/newmem
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2006-10-02
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-10-02
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2006-10-02
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-10-02
Kevin Lim
Updates to fix merge issues and bring almost everything...
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2006-10-01
Kevin Lim
Merge ktlim@zamp:./local/clean/o3-merge/m5
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2006-07-19
Ali Saidi
Merge zizzer:/bk/newmem
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2006-07-18
Gabe Black
Merge m5.eecs.umich.edu:/bk/newmem
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2006-07-11
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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