Revert power patch sets with unexpected interactions
[gem5.git] / src / cpu / base_dyn_inst.hh
2016-04-06 Andreas SandbergRevert power patch sets with unexpected interactions
2016-04-05 Mitch Hayengamem: Remove threadId from memory request class
2016-01-18 Steve Reinhardtcpu. arch: add initiateMemRead() to ExecContext interface
2016-01-18 Steve Reinhardtcpu: remove unnecessary data ptr from O3 internal read...
2016-01-11 Andreas Hanssonscons: Enable -Wextra by default
2015-09-30 Mitch Hayengacpu: Add per-thread monitors
2015-09-15 Hongil Yooncpu, o3: consider split requests for LSQ checksnoop...
2015-08-07 Andreas Sandbergbase: Declare a type for context IDs
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2015-05-15 Andreas Hanssonmisc: Appease gcc 5.1
2015-05-05 Andreas Sandbergmem, cpu: Add a separate flag for strictly ordered...
2015-03-02 Rekaicpu: o3 register renaming request handling improved
2015-02-11 Andreas Sandbergsim: Move the BaseTLB to src/arch/generic/
2015-01-25 Ali Saidisim: Clean up InstRecord
2014-11-06 Marc Orrx86 isa: This patch attempts an implementation at mwait.
2014-10-16 Andreas Hanssonarch: Use shared_ptr for all Faults
2014-09-27 Andreas Hanssonarch: Use const StaticInstPtr references where possible
2014-09-03 Andreas Sandbergarch, cpu: Factor out the ExecContext into a proper...
2014-05-09 Akash Bagdiacpu, arm: Allow the specification of a socket field
2014-03-07 Andreas Hanssoncpu: Make CPU and ThreadContext getters const
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when...
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2013-10-17 Ali Saidicpu: Fix O3 uncacheable load that is replayed but misse...
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2012-06-05 Ali SaidiO3: Clean up the O3 structures and try to pack them...
2012-06-05 Ali Saidisim: Remove FastAlloc
2012-03-19 Andreas Hanssongcc: Clean-up of non-C++0x compliant code, first steps
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-07 Gabe BlackFaults: Turn off arch/faults.hh
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-18 Gabe BlackSE/FS: Get rid of includes of config/full_system.hh.
2011-09-13 Ali SaidiLSQ: Only trigger a memory violation with a load/load...
2011-09-09 Gabe BlackStaticInst: Merge StaticInst and StaticInstBase.
2011-08-14 Gabe BlackO3: Add a pointer to the macroop for a microop in the...
2011-08-07 Gabe BlackTranslation: Use a pointer type as the template argument.
2011-08-02 Gabe BlackO3: Get rid of the raw ExtMachInst constructor on DynInsts.
2011-07-03 Nilay VaishMerged with Gabe's recent changes.
2011-07-03 Gabe BlackExecContext: Rename the readBytes/writeBytes functions...
2011-07-03 Gabe BlackExecContext: Get rid of the now unused read/write templ...
2011-04-04 Ali SaidiCPU: Remove references to memory copy operations
2011-04-04 Ali SaidiO3: Tighten memory order violation checking to 16 bytes.
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-12 Giacomo GabrielliO3: Enhance data address translation by supporting...
2010-12-08 Ali SaidiO3: Support squashing all state after special instruction
2010-12-08 Giacomo GabrielliO3: Make all instructions that write a misc. register...
2010-11-08 Ali SaidiARM/Alpha/Cpu: Change prefetchs to be more like normal...
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-23 Min Kyu JeongCPU: Make Exec trace to print predication result (if...
2010-08-23 Min Kyu JeongARM/O3: store the result of the predicate evaluation...
2010-08-23 Ali SaidiCPU: Set a default value when readBytes faults.
2010-08-13 Gabe BlackMerge with head.
2010-08-13 Gabe BlackCPU: Add readBytes and writeBytes functions to the...
2010-02-20 Timothy M. JonesBaseDynInst: Preserve the faults returned from read...
2010-02-12 Timothy M. JonesO3PCU: Split loads and stores that cross cache line...
2010-02-12 Timothy M. JonesBaseDynInst: Make the TLB translation timing instead...
2010-01-19 Derek Howermerge
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtFix setting of INST_FETCH flag for O3 CPU.
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-04-09 Nathan Binkerttlb: More fixing of unified TLB
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-02-25 Gabe BlackISA: Replace the translate functions in the TLBs with...
2009-02-25 Gabe BlackCPU: Get rid of translate... functions from various...
2008-11-10 Clint SmullenO3CPU: Make the instcount debugging stuff per-cpu.
2008-11-03 Lisa HsuAdd in Context IDs to the simulator. From now on,...
2008-11-03 Lisa Hsumake BaseCPU the provider of _cpuId, and cpuId() instea...
2008-09-10 Ali Saidistyle: Remove non-leading tabs everywhere they shouldn...
2008-02-27 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-02-27 Gabe BlackTLB: Make a TLB base class and put a virtual demapPage...
2007-10-31 Steve ReinhardtMerge in bus DPRINTF changes.
2007-10-22 Gabe BlackMerge with head.
2007-10-22 Gabe BlackCPU: Add functions to the "ExecContext"s that translate...
2007-08-28 Gabe BlackMerge with head.
2007-08-27 Gabe BlackO3 CPU: Remove alignment check from dynamic instruction...
2007-08-01 Gabe BlackMerge with head.
2007-08-01 Ali SaidiMerge Gabe and my changes to arch/mips/utility.hh
2007-08-01 Gabe BlackMerge with head.
2007-08-01 Gabe BlackAdd a flag to indicate an instruction triggers a syscal...
2007-06-22 Steve ReinhardtMerge vm1.(none):/home/stever/bk/newmem-head
2007-06-22 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-06-21 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-06-21 Gabe BlackFix compiler errors.
2007-06-20 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-10 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-10 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
next