cpu: o3: combine if with same condition
[gem5.git] / src / cpu / checker /
2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout
2015-02-11 Andreas Sandbergsim: Move the BaseTLB to src/arch/generic/
2015-01-25 Ali Saidicpu: Remove all notion that we know when the cpu is...
2015-01-22 Andreas Hanssonmem: Clean up Request initialisation
2014-11-06 Marc Orrx86 isa: This patch attempts an implementation at mwait.
2014-10-30 Ali Saidiautomated merge
2014-10-30 Ali Saidicpu: Add support to checker for CACHE_BLOCK_ZERO commands.
2014-10-09 Mitch Hayengacpu: Remove Ozone CPU from the source tree
2014-09-27 Andreas Hanssonarch: Use const StaticInstPtr references where possible
2014-09-27 Andreas Hanssonscons: Address issues related to gcc 4.9.1
2014-09-20 Mitch Hayengaalpha,arm,mips,power,x86,cpu,sim: Cleanup activate...
2014-09-19 Andreas Hanssonarch: Pass faults by const reference where possible
2014-09-12 Andrew Bardsleystyle: Fix line continuation, especially in debug messages
2014-05-13 Curtis Dunhammem: Refactor assignment of Packet types
2014-09-03 Andreas Sandbergarch, cpu: Factor out the ExecContext into a proper...
2014-05-09 Akash Bagdiacpu, arm: Allow the specification of a socket field
2014-03-07 Andreas Hanssoncpu: Make CPU and ThreadContext getters const
2014-01-24 Geoffrey Blakechecker: CheckerCPU handling of MiscRegs was incorrect
2014-01-24 Ali Saidiarch, cpu: Add support for flattening misc register...
2013-11-15 Andreas Hanssoncpu: Fix Checker register index use
2013-10-17 Matt Horsnellcpu: add consistent guarding to *_impl.hh files.
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-10-15 Steve Reinhardtcpu: rename *_DepTag constants to *_Reg_Base
2013-10-15 Steve Reinhardtcpu: clean up architectural register classification
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-03-26 Andreas Hanssoncpu: Remove CpuPort and use MasterPort in the CPU classes
2013-01-07 Andreas Sandbergcpu: Implement a flat register interface in thread...
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2013-01-07 Ali Saidicpu: rename the misleading inSyscall to noSquashFromTC
2013-01-05 Gabe BlackDecoder: Remove the thread context get/set from the...
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonChecker: Fix checker CPU ports
2012-05-26 Gabe BlackCPU: Merge the predecoder and decoder.
2012-05-25 Gabe BlackDecode: Make the Decoder class defined per ISA.
2012-05-10 Ali Saidigem5: fix a number of use after free issues
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-09 Geoffrey BlakeCheckerCPU: Add function stubs to non-ARM ISA source...
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-02 Andreas HanssonCPU: Check that the interrupt controller is created...
2012-02-24 Andreas HanssonMEM: Make port proxies use references rather than pointers
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-07 Gabe BlackChecker: Access workload element 0 only if there is...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonMEM: Add port proxies instead of non-structural ports
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-18 Gabe BlackSE/FS: Get rid of includes of config/full_system.hh.
2011-11-18 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-10-30 Gabe BlackSE/FS: Make getProcessPtr available in both modes,...
2011-10-16 Gabe BlackSE/FS: Include getMemPort in FS.
2011-10-16 Gabe BlackSE/FS: Build/expose vport in SE mode.
2011-10-16 Gabe BlackCPU: Make physPort and getPhysPort available in SE...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-11-08 Ali SaidiARM/Alpha/Cpu: Change prefetchs to be more like normal...
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-09-14 Gabe BlackCPU: Get rid of the now unnecessary getInst/setInst...
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-31 Gabe BlackCPU: Get rid of the unused ev5_trap function on the...
2010-06-03 Steve ReinhardtMinor remote GDB cleanup.
2010-02-27 Nathan Binkertcpu_models: get rid of cpu_models.py and move the stuff...
2010-01-19 Derek Howermerge
2009-11-11 Gabe BlackMerge with the head.
2009-11-11 Gabe BlackMem: Eliminate the NO_FAULT request flag.
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-07-13 Derek Howermerge
2009-07-09 Gabe BlackGet rid of the unused get(Data|Inst)Asid and (inst...
2009-07-09 Gabe BlackRegisters: Get rid of the float register width parameter.
2009-04-20 Gabe BlackMem: Change isLlsc to isLLSC.
2009-04-19 Gabe BlackMemory: Rename LOCKED for load locked store conditional...
2009-04-15 Steve ReinhardtThreadState: initialize status to Halted in constructor.
2009-04-15 Steve ReinhardtGet rid of the Unallocated thread context state.
2009-04-09 Gabe Blacktlb: Don't separate the TLB classes into an instruction...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-02-27 Gabe BlackProcesses: Make getting and setting system call argumen...
2009-02-25 Gabe BlackISA: Replace the translate functions in the TLBs with...
2009-02-25 Gabe BlackCPU: Get rid of translate... functions from various...
2008-11-04 Lisa Hsuget rid of all instances of readTid() and getThreadNum...
2008-11-03 Lisa HsuAdd in Context IDs to the simulator. From now on,...
2008-11-03 Lisa Hsumake BaseCPU the provider of _cpuId, and cpuId() instea...
2008-10-20 Ali SaidiO3CPU: Undo Gabe's changes to remove hwrei and simpalch...
2008-10-13 Gabe BlackGet rid of old RegContext code.
2008-10-11 Gabe BlackCPU: Eliminate the simPalCheck funciton.
2008-10-11 Gabe BlackCPU: Eliminate the hwrei function.
2008-09-10 Ali Saidistyle: Remove non-leading tabs everywhere they shouldn...
2008-08-11 Nathan Binkertparams: Convert the CPU objects to use the auto generat...
2008-07-01 Ali SaidiRemove delVirtPort() and make getVirtPort() only return...
2008-02-27 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-02-27 Gabe BlackTLB: Make a TLB base class and put a virtual demapPage...
2007-08-28 Gabe BlackMerge with head.
2007-08-27 Gabe BlackAddress Translation: Make SE mode use an actual TLB...
2007-03-23 Kevin LimMerge ktlim@zizzer:/bk/newmem
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