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cpu: Update DRAM traffic gen
[gem5.git]
/
src
/
cpu
/
inorder
/
InOrderCPU.py
2014-03-02
Christopher Torng
cpu: Enable fast-forwarding for MIPS InOrderCPU and...
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2013-09-04
Andreas Hansson
cpu: Move the branch predictor out of the BaseCPU
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2013-02-15
Andreas Sandberg
cpu: Add CPU metadata om the Python classes
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2013-01-24
Nilay Vaish ext...
branch predictor: move out of o3 and inorder cpus
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2012-11-02
Andreas Sandberg
sim: Include object header files in SWIG interfaces
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2012-09-07
Andreas Hansson
Param: Transition to Cycles for relevant parameters
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2012-08-21
Andreas Hansson
CPU: Remove overloaded function_trace_start parameter
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2012-02-24
Andreas Hansson
CPU: Round-two unifying instr/data CPU ports across...
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-17
Andreas Hansson
CPU: Moving towards a more general port across CPU...
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2011-02-04
Korey Sewell
inorder: add a fetch buffer to fetch unit
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2011-02-04
Korey Sewell
inorder: stage width as a python parameter
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2011-02-04
Gabe Black
Config: Keep track of uncached and cached ports separately.
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2010-02-01
Brad Beckmann
merge
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2010-01-31
Korey Sewell
configs/inorder: add options for switch-on-miss to...
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2010-01-19
Derek Hower
merge
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2009-09-22
Nathan Binkert
python: Move more code into m5.util allow SCons to...
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2009-04-06
Gabe Black
Merge ARM into the head. ARM will compile but may not...
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2009-03-04
Korey Sewell
InOrder didnt have all it's params set to a default...
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2009-02-10
Korey Sewell
InOrder: Import new inorder CPU model from MIPS.
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