git.libre-soc.org Git - gem5.git/history

2019-08-28	Gabe Black	cpu: Make get(Data\|Inst)Port return a Port and not...	blob \| commitdiff \| raw
2019-05-14	Giacomo Travaglini	Revert "cpu: fix how a thread starts up in MinorCPU"	blob \| commitdiff \| raw \| diff to current
2019-02-06	Tuan Ta	cpu: fix how a thread starts up in MinorCPU	blob \| commitdiff \| raw \| diff to current
2016-07-21	Mitch Hayenga	cpu: Add SMT support to MinorCPU	blob \| commitdiff \| raw \| diff to current
2016-02-10	Andreas Hansson	mem: Deduce if cache should forward snoops	blob \| commitdiff \| raw \| diff to current
2015-10-12	Andreas Hansson	misc: Add explicit overrides and fix other clang >...	blob \| commitdiff \| raw \| diff to current
2015-10-12	Andreas Hansson	misc: Remove redundant compiler-specific defines	blob \| commitdiff \| raw \| diff to current
2015-09-30	Mitch Hayenga	cpu,isa,mem: Add per-thread wakeup logic	blob \| commitdiff \| raw \| diff to current
2015-07-07	Andreas Sandberg	sim: Refactor and simplify the drain API	blob \| commitdiff \| raw \| diff to current
2015-07-07	Andreas Sandberg	sim: Refactor the serialization base class	blob \| commitdiff \| raw \| diff to current
2014-09-20	Mitch Hayenga	alpha,arm,mips,power,x86,cpu,sim: Cleanup activate...	blob \| commitdiff \| raw \| diff to current
2014-07-23	Andrew Bardsley	cpu: `Minor' in-order CPU model	blob \| commitdiff \| raw \| diff to current