git.libre-soc.org Git - gem5.git/history - src/cpu/o3/FuncUnitConfig.py

2019-03-14	Giacomo Gabrielli	arch-arm,cpu: Add initial support for Arm SVE	blob \| commitdiff \| raw
2019-02-12	Andreas Sandberg	python: Don't assume SimObjects live in the global...	blob \| commitdiff \| raw \| diff to current
2016-10-15	Fernando Endo	cpu, arm: Distinguish Float* and SimdFloat*, create...	blob \| commitdiff \| raw \| diff to current
2015-04-30	Nilay Vaish	cpu: o3: replace issueLatency with bool pipelined	blob \| commitdiff \| raw \| diff to current
2015-04-30	Nilay Vaish	cpu: o3: single cycle default div microop latency on x86	blob \| commitdiff \| raw \| diff to current
2010-11-15	Giacomo Gabrielli	CPU/ARM: Add SIMD op classes to CPU models and ARM...	blob \| commitdiff \| raw \| diff to current
2007-06-20	Gabe Black	Merge zizzer.eecs.umich.edu:/bk/newmem	blob \| commitdiff \| raw \| diff to current
2007-05-31	Gabe Black	Merge zizzer.eecs.umich.edu:/bk/newmem	blob \| commitdiff \| raw \| diff to current
2007-05-28	Steve Reinhardt	Merge vm1.(none):/home/stever/bk/newmem-head	blob \| commitdiff \| raw \| diff to current
2007-05-28	Nathan Binkert	Move SimObject python files alongside the C++ and fix	blob \| commitdiff \| raw \| diff to current