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cpu: make ExecSymbol show the symbol in addition to address
[gem5.git]
/
src
/
cpu
/
o3
/
O3CPU.py
2020-02-26
Bobby R. Bruce
misc: merge branch 'release-staging-v19.0.0.0' into...
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2020-02-24
Bobby R. Bruce
misc: Merged release-staging-v19.0.0.0 into develop
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2020-02-17
Gabe Black
cpu: Delete authors lists from the cpu directory.
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2019-10-23
Gabe Black
cpu: Apply the ARM TLB rework to the O3 checker CPU.
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2019-02-22
Gabor Dozsa
cpu-o3: Add cache read ports limit to LSQ
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2019-02-12
Andreas Sandberg
python: Don't assume SimObjects live in the global...
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2019-01-30
Giacomo Gabrielli
arch,cpu: Add vector predicate registers
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2019-01-17
Nikos Nikoleris
cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum
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2019-01-17
Nikos Nikoleris
cpu-o3: Make the smtROBPolicy a Param.ScopedEnum
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2019-01-17
Nikos Nikoleris
cpu-o3: Make the smtIQPolicy a Param.ScopedEnum
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2019-01-17
Nikos Nikoleris
cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum
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2019-01-17
Nikos Nikoleris
cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum
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2018-03-06
Gabe Black
scons: Switch from the print statement to the print...
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2017-07-05
Rekai Gonzalez-Alb...
cpu: Added interface for vector reg file
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2016-12-21
Arthur Perais
cpu: Clarify meaning of cachePorts variable in lsq_unit...
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2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
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2015-07-26
Nilay Vaish
cpu: implements vector registers
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2015-04-13
Dibakar Gope
cpu: re-organizes the branch predictor structure.
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2014-04-29
Curtis Dunham
arm: use condition code registers for ARM ISA
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2014-09-03
Mitch Hayenga
cpu: Fix SMT scheduling issue with the O3 cpu
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2014-09-03
Mitch Hayenga
cpu: Add a fetch queue to the o3 cpu
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2014-09-03
Mitch Hayenga
cpu: Change writeback modeling for outstanding instructions
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2013-11-15
Anthony Gutierrez
cpu: allow the fetch buffer to be smaller than a cache...
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2013-10-15
Yasuko Eckert
arch/x86: add support for explicit CC register file
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2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
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2013-09-04
Andreas Hansson
cpu: Move the branch predictor out of the BaseCPU
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2013-02-15
Andreas Sandberg
cpu: Add CPU metadata om the Python classes
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2013-01-24
Nilay Vaish ext...
branch predictor: move out of o3 and inorder cpus
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2012-11-02
Andreas Sandberg
cpu: O3 add a header declaring the DerivO3CPU
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2012-09-07
Andreas Hansson
Param: Transition to Cycles for relevant parameters
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2012-08-28
Andreas Hansson
Clock: Rework clocks to avoid tick-to-cycle transformations
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2012-07-27
Anthony Gutierrez
checker: make checker cpu id match its host's cpu id
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2012-03-09
Geoffrey Blake
CheckerCPU: Make CheckerCPU runtime selectable instead...
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Geoffrey Blake
CheckerCPU: Re-factor CheckerCPU to be compatible with...
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2012-01-31
Gabe Black
Merge with main repository.
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2012-01-29
Gabe Black
Yet another merge with the main repository.
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2012-01-29
Nilay Vaish
O3 CPU LSQ: Implement TSO
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-16
Gabe Black
Merge yet again with the main repository.
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2012-01-17
Andreas Hansson
CPU: Moving towards a more general port across CPU...
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2012-01-07
Gabe Black
Another merge with the main repository.
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2012-01-07
Gabe Black
Merge with the main repository again.
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2012-01-07
Gabe Black
Merge with main repository.
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2011-12-01
Chander Sudanthi
O3: Remove hardcoded tgts_per_mshr in O3CPU.py.
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2011-11-18
Gabe Black
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
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2011-08-19
Ali Saidi
LSQ: Set store predictor to periodically clear itself...
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2011-04-04
Ali Saidi
O3: Tighten memory order violation checking to 16 bytes.
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2011-02-04
Gabe Black
Config: Keep track of uncached and cached ports separately.
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2011-02-02
Gabe Black
X86: Add L1 caches for the TLB walkers.
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2010-01-19
Derek Hower
merge
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2009-09-22
Nathan Binkert
python: Move more code into m5.util allow SCons to...
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2009-04-06
Gabe Black
Merge ARM into the head. ARM will compile but may not...
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2008-08-11
Nathan Binkert
params: Convert the CPU objects to use the auto generat...
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2007-11-15
Korey Sewell
branch merge
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2007-11-12
Gabe Black
X86: Implement a page table walker.
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2007-08-28
Gabe Black
Merge with head.
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2007-08-27
Gabe Black
Address Translation: Make SE mode use an actual TLB...
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2007-06-21
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-06-21
Steve Reinhardt
Merge vm1.(none):/home/stever/bk/newmem-head
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2007-06-20
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-06-20
Nathan Binkert
Make sure all parameters have default values if they're
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2007-06-20
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-05-31
Gabe Black
Merge zizzer.eecs.umich.edu:/bk/newmem
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2007-05-28
Steve Reinhardt
Merge vm1.(none):/home/stever/bk/newmem-head
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2007-05-28
Nathan Binkert
Move SimObject python files alongside the C++ and fix
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