arch/x86: add support for explicit CC register file
[gem5.git] / src / cpu / o3 / O3CPU.py
2013-10-15 Yasuko Eckertarch/x86: add support for explicit CC register file
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-09-04 Andreas Hanssoncpu: Move the branch predictor out of the BaseCPU
2013-02-15 Andreas Sandbergcpu: Add CPU metadata om the Python classes
2013-01-24 Nilay Vaish ext... branch predictor: move out of o3 and inorder cpus
2012-11-02 Andreas Sandbergcpu: O3 add a header declaring the DerivO3CPU
2012-09-07 Andreas HanssonParam: Transition to Cycles for relevant parameters
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-07-27 Anthony Gutierrezchecker: make checker cpu id match its host's cpu id
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-29 Nilay VaishO3 CPU LSQ: Implement TSO
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonCPU: Moving towards a more general port across CPU...
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-12-01 Chander SudanthiO3: Remove hardcoded tgts_per_mshr in O3CPU.py.
2011-11-18 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-08-19 Ali SaidiLSQ: Set store predictor to periodically clear itself...
2011-04-04 Ali SaidiO3: Tighten memory order violation checking to 16 bytes.
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately.
2011-02-02 Gabe BlackX86: Add L1 caches for the TLB walkers.
2010-01-19 Derek Howermerge
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2008-08-11 Nathan Binkertparams: Convert the CPU objects to use the auto generat...
2007-11-15 Korey Sewellbranch merge
2007-11-12 Gabe BlackX86: Implement a page table walker.
2007-08-28 Gabe BlackMerge with head.
2007-08-27 Gabe BlackAddress Translation: Make SE mode use an actual TLB...
2007-06-21 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-06-21 Steve ReinhardtMerge vm1.(none):/home/stever/bk/newmem-head
2007-06-20 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-06-20 Nathan BinkertMake sure all parameters have default values if they're
2007-06-20 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-31 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-28 Steve ReinhardtMerge vm1.(none):/home/stever/bk/newmem-head
2007-05-28 Nathan BinkertMove SimObject python files alongside the C++ and fix