2019-10-15 |
Gabe Black | sim,cpu: Get rid of the unused instEventQueue. |
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2019-08-28 |
Gabe Black | cpu: Move the instruction port into o3's fetch stage. |
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2019-08-28 |
Gabe Black | cpu: Move O3's data port into the LSQ. |
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2019-07-16 |
Giacomo Travaglini | cpu: isDrained renamed to isCpuDrained |
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2019-05-18 |
Gabe Black | arch, base, cpu, dev, mem, sim: Remove #if 0-ed out... |
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2019-04-30 |
Gabe Black | cpu: alpha: Delete all occurrances of the simPalCheck... |
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2019-04-30 |
Gabe Black | cpu: Remove hwrei from the generic interfaces. |
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2019-04-30 |
Gabe Black | arch: cpu: Track kernel stats using the base ISA agnost... |
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2019-04-03 |
Andrea Mondelli | misc: Removed inconsistency in O3* debug msgs |
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2019-03-28 |
Javier Bueno | cpu: Added a probe to notify the address of retired... |
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2019-02-08 |
Tuan Ta | sim,cpu: make exit_group halt all threads in a group |
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2019-02-08 |
Tuan Ta | cpu: fixed how O3 CPU executes an exit system call |
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2019-02-01 |
Gabe Black | cpu, arch: Replace the CCReg type with RegVal. |
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2019-01-31 |
Gabe Black | arch: cpu: Rename *FloatRegBits* to *FloatReg*. |
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2019-01-30 |
Giacomo Gabrielli | arch,cpu: Add vector predicate registers |
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2019-01-25 |
Giacomo Travaglini | cpu, arch, arch-arm: Wire unused VecElem code in the... |
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2019-01-25 |
Giacomo Travaglini | cpu: Fix VecElemClass bugs in cpu models |
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2019-01-24 |
Rekai Gonzalez-Alb... | cpu-o3: O3 LSQ Generalisation |
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2019-01-22 |
Gabe Black | arch: cpu: Stop passing around misc registers by reference. |
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2019-01-16 |
Gabe Black | cpu: dev: sim: gpu-compute: Banish some ISA specific... |
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2019-01-15 |
Giacomo Travaglini | cpu: Fix usage of setArchVecElem |
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2018-12-20 |
Gabe Black | arch, cpu: Remove float type accessors. |
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2018-11-16 |
Rekai Gonzalez-Alb... | cpu: Fix the usage of const DynInstPtr |
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2017-11-21 |
Jose Marinho | cpu, cpu, sim: move Cycle probe update |
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2017-11-20 |
Anouk Van Laer | pwr: Adds logic to enter power gating for the cpu model |
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2017-07-17 |
Anouk Van Laer | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU |
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2017-07-12 |
Sean Wilson | cpu: Refactor some Event subclasses to lambdas |
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2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Added interface for vector reg file |
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2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Simplify the rename interface and use RegId |
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2017-07-05 |
Nathanael Premillieu | cpu: Physical register structural + flat indexing |
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2017-07-05 |
Nathanael Premillieu | arch, cpu: Architectural Register structural indexing |
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2015-07-20 |
Brandon Potter | syscall_emul: [patch 13/22] add system call retry capab... |
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2016-11-09 |
Brandon Potter | style: [patch 1/22] use /r/3648/ to reorganize includes |
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2016-09-14 |
Michael LeBeane | sim: Refactor quiesce and remove FS asserts |
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2016-06-06 |
David Guillen Fandos | pwr: Low-power idle power state for idle CPUs |
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2016-04-06 |
Andreas Sandberg | Revert power patch sets with unexpected interactions |
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2014-12-09 |
Akash Bagdia | power: Low-power idle power state for idle CPUs |
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2015-12-31 |
Andreas Hansson | mem: Make cache terminology easier to understand |
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2015-12-07 |
Radhika Jagtap | probe: Add probe in Fetch, IEW, Rename and Commit |
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2015-11-22 |
Nathanael Premillieu | cpu: Fix base FP and CC register index in o3 insertThread() |
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2015-09-30 |
Mitch Hayenga | cpu,isa,mem: Add per-thread wakeup logic |
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2015-09-30 |
Mitch Hayenga | isa,cpu: Add support for FS SMT Interrupts |
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2015-09-30 |
Mitch Hayenga | cpu: Add per-thread monitors |
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2015-07-28 |
Nilay Vaish | revert 5af8f40d8f2c |
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2015-07-26 |
Nilay Vaish | cpu: implements vector registers |
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2015-07-07 |
Andreas Sandberg | sim: Refactor and simplify the drain API |
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2015-07-07 |
Andreas Sandberg | sim: Make the drain state a global typed enum |
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2015-07-07 |
Andreas Sandberg | sim: Refactor the serialization base class |
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2015-05-05 |
Andreas Hansson | mem: Snoop into caches on uncacheable accesses |
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2015-04-03 |
Nikos Nikoleris | cpu: fix system total instructions accounting |
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2015-03-02 |
Andreas Hansson | mem: Split port retry for all different packet classes |
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2015-02-16 |
Andreas Hansson | arch: Make readMiscRegNoEffect const throughout |
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2015-02-07 |
Alexandru Dutu | cpu: Idle CPU status logic revised |
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2014-11-06 |
Marc Orr | x86 isa: This patch attempts an implementation at mwait. |
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2014-10-20 |
Nilay Vaish | cpu: o3: corrects base FP and CC register index in... |
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2014-10-16 |
Andreas Sandberg | cpu: Probe points for basic PMU stats |
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2014-09-27 |
Andreas Hansson | arch: Use const StaticInstPtr references where possible |
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2014-09-20 |
Mitch Hayenga | cpu: Remove unused deallocateContext calls |
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2014-09-20 |
Mitch Hayenga | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate... |
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2014-09-19 |
Andreas Hansson | arch: Pass faults by const reference where possible |
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2014-09-03 |
Mitch Hayenga | cpu: Fix SMT scheduling issue with the O3 cpu |
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2014-06-21 |
Binh Pham | o3: split load & store queue full cases in rename |
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2014-05-23 |
Nilay Vaish | cpu: o3: remove stat totalCommittedInsts |
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2014-04-19 |
Faissal Sleiman | o3: Fix occupancy checks for SMT |
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2014-01-24 |
Matt Horsnell | base: add support for probe points and common probes |
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2013-12-03 |
Nilay Vaish | cpu: call BaseCPU startup() function in o3 cpu |
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2013-10-31 |
Faissal Sleiman | cpu: Construct ROB with cpu params struct instead of... |
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2013-10-15 |
Yasuko Eckert | cpu: add a condition-code register class |
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2013-10-15 |
Steve Reinhardt | cpu/o3: clean up rename map and free list |
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2013-10-15 |
Steve Reinhardt | cpu/o3: clean up scoreboard object |
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2013-10-15 |
Steve Reinhardt | cpu/o3: clean up physical register file |
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2013-04-22 |
Dam Sunwoo | sim: separate nextCycle() and clockEdge() in clockedObjects |
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2013-02-15 |
Andreas Sandberg | sim: Add a system-global option to bypass caches |
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2013-02-15 |
Andreas Sandberg | cpu: Refactor memory system checks |
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2013-01-13 |
Nilay Vaish | x86: Changes to decoder, corrects 9376 |
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2013-01-07 |
Andreas Sandberg | cpu: Unify the serialization code for all of the CPU... |
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2013-01-07 |
Andreas Sandberg | cpu: Rewrite O3 draining to avoid stopping in microcode |
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2013-01-07 |
Andreas Sandberg | o3 cpu: Remove unused variables |
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2013-01-07 |
Andreas Sandberg | cpu: Rename defer_registration->switched_out |
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2013-01-07 |
Andreas Sandberg | cpu: Correctly call parent on switchOut() and takeOverF... |
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2013-01-07 |
Andreas Sandberg | cpu: Unify SimpleCPU and O3 CPU serialization code |
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2013-01-07 |
Andreas Sandberg | cpu: Initialize the O3 pipeline from startup() |
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2013-01-07 |
Andreas Sandberg | cpu: Check that the memory system is in the correct... |
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2013-01-07 |
Andreas Sandberg | arch: Make the ISA class inherit from SimObject |
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2013-01-07 |
Ali Saidi | cpu: rename the misleading inSyscall to noSquashFromTC |
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2012-11-02 |
Andreas Sandberg | sim: Move the draining interface into a separate base... |
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2012-08-28 |
Andreas Hansson | Clock: Add a Cycles wrapper class and use where applicable |
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2012-08-28 |
Andreas Hansson | Clock: Rework clocks to avoid tick-to-cycle transformations |
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2012-08-21 |
Andreas Hansson | Clock: Make Tick unsigned and remove UTick |
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2012-08-15 |
Anthony Gutierrez | O3,ARM: fix some problems with drain/switchout function... |
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2012-05-01 |
Andreas Hansson | MEM: Separate requests and responses for timing accesses |
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2012-04-14 |
Andreas Hansson | MEM: Separate snoops and normal memory requests/responses |
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2012-03-30 |
Andreas Hansson | CPU: Unify initMemProxies across CPUs and simulation... |
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2012-03-09 |
Geoffrey Blake | CheckerCPU: Make CheckerCPU runtime selectable instead... |
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2012-03-02 |
Andreas Hansson | CPU: Check that the interrupt controller is created... |
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2012-03-01 |
Nilay Vaish | x86: Fix switching of CPUs |
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2012-02-24 |
Andreas Hansson | CPU: Round-two unifying instr/data CPU ports across... |
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2012-02-12 |
Anthony Gutierrez | cpu: add separate stats for insts/ops both globally... |
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2012-02-01 |
Gabe Black | Merge ... head, hopefully the last time for this batch. |
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2012-01-31 |
Koan-Sin Tan | clang: Enable compiling gem5 using clang 2.9 and 3.0 |
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