arch: Get rid of the unused GenericTLB.
[gem5.git] / src / cpu / o3 / cpu.cc
2019-10-15 Gabe Blacksim,cpu: Get rid of the unused instEventQueue.
2019-08-28 Gabe Blackcpu: Move the instruction port into o3's fetch stage.
2019-08-28 Gabe Blackcpu: Move O3's data port into the LSQ.
2019-07-16 Giacomo Travaglinicpu: isDrained renamed to isCpuDrained
2019-05-18 Gabe Blackarch, base, cpu, dev, mem, sim: Remove #if 0-ed out...
2019-04-30 Gabe Blackcpu: alpha: Delete all occurrances of the simPalCheck...
2019-04-30 Gabe Blackcpu: Remove hwrei from the generic interfaces.
2019-04-30 Gabe Blackarch: cpu: Track kernel stats using the base ISA agnost...
2019-04-03 Andrea Mondellimisc: Removed inconsistency in O3* debug msgs
2019-03-28 Javier Buenocpu: Added a probe to notify the address of retired...
2019-02-08 Tuan Tasim,cpu: make exit_group halt all threads in a group
2019-02-08 Tuan Tacpu: fixed how O3 CPU executes an exit system call
2019-02-01 Gabe Blackcpu, arch: Replace the CCReg type with RegVal.
2019-01-31 Gabe Blackarch: cpu: Rename *FloatRegBits* to *FloatReg*.
2019-01-30 Giacomo Gabrielliarch,cpu: Add vector predicate registers
2019-01-25 Giacomo Travaglinicpu, arch, arch-arm: Wire unused VecElem code in the...
2019-01-25 Giacomo Travaglinicpu: Fix VecElemClass bugs in cpu models
2019-01-24 Rekai Gonzalez-Alb... cpu-o3: O3 LSQ Generalisation
2019-01-22 Gabe Blackarch: cpu: Stop passing around misc registers by reference.
2019-01-16 Gabe Blackcpu: dev: sim: gpu-compute: Banish some ISA specific...
2019-01-15 Giacomo Travaglinicpu: Fix usage of setArchVecElem
2018-12-20 Gabe Blackarch, cpu: Remove float type accessors.
2018-11-16 Rekai Gonzalez-Alb... cpu: Fix the usage of const DynInstPtr
2017-11-21 Jose Marinhocpu, cpu, sim: move Cycle probe update
2017-11-20 Anouk Van Laerpwr: Adds logic to enter power gating for the cpu model
2017-07-17 Anouk Van Laercpu,o3: Fixed checkpointing bug occuring in the o3 CPU
2017-07-12 Sean Wilsoncpu: Refactor some Event subclasses to lambdas
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file
2017-07-05 Rekai Gonzalez-Alb... cpu: Simplify the rename interface and use RegId
2017-07-05 Nathanael Premillieucpu: Physical register structural + flat indexing
2017-07-05 Nathanael Premillieuarch, cpu: Architectural Register structural indexing
2015-07-20 Brandon Pottersyscall_emul: [patch 13/22] add system call retry capab...
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2016-09-14 Michael LeBeanesim: Refactor quiesce and remove FS asserts
2016-06-06 David Guillen Fandospwr: Low-power idle power state for idle CPUs
2016-04-06 Andreas SandbergRevert power patch sets with unexpected interactions
2014-12-09 Akash Bagdiapower: Low-power idle power state for idle CPUs
2015-12-31 Andreas Hanssonmem: Make cache terminology easier to understand
2015-12-07 Radhika Jagtapprobe: Add probe in Fetch, IEW, Rename and Commit
2015-11-22 Nathanael Premillieucpu: Fix base FP and CC register index in o3 insertThread()
2015-09-30 Mitch Hayengacpu,isa,mem: Add per-thread wakeup logic
2015-09-30 Mitch Hayengaisa,cpu: Add support for FS SMT Interrupts
2015-09-30 Mitch Hayengacpu: Add per-thread monitors
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c
2015-07-26 Nilay Vaishcpu: implements vector registers
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API
2015-07-07 Andreas Sandbergsim: Make the drain state a global typed enum
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class
2015-05-05 Andreas Hanssonmem: Snoop into caches on uncacheable accesses
2015-04-03 Nikos Nikoleriscpu: fix system total instructions accounting
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout
2015-02-07 Alexandru Dutucpu: Idle CPU status logic revised
2014-11-06 Marc Orrx86 isa: This patch attempts an implementation at mwait.
2014-10-20 Nilay Vaishcpu: o3: corrects base FP and CC register index in...
2014-10-16 Andreas Sandbergcpu: Probe points for basic PMU stats
2014-09-27 Andreas Hanssonarch: Use const StaticInstPtr references where possible
2014-09-20 Mitch Hayengacpu: Remove unused deallocateContext calls
2014-09-20 Mitch Hayengaalpha,arm,mips,power,x86,cpu,sim: Cleanup activate...
2014-09-19 Andreas Hanssonarch: Pass faults by const reference where possible
2014-09-03 Mitch Hayengacpu: Fix SMT scheduling issue with the O3 cpu
2014-06-21 Binh Phamo3: split load & store queue full cases in rename
2014-05-23 Nilay Vaishcpu: o3: remove stat totalCommittedInsts
2014-04-19 Faissal Sleimano3: Fix occupancy checks for SMT
2014-01-24 Matt Horsnellbase: add support for probe points and common probes
2013-12-03 Nilay Vaishcpu: call BaseCPU startup() function in o3 cpu
2013-10-31 Faissal Sleimancpu: Construct ROB with cpu params struct instead of...
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-10-15 Steve Reinhardtcpu/o3: clean up rename map and free list
2013-10-15 Steve Reinhardtcpu/o3: clean up scoreboard object
2013-10-15 Steve Reinhardtcpu/o3: clean up physical register file
2013-04-22 Dam Sunwoosim: separate nextCycle() and clockEdge() in clockedObjects
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-02-15 Andreas Sandbergcpu: Refactor memory system checks
2013-01-13 Nilay Vaishx86: Changes to decoder, corrects 9376
2013-01-07 Andreas Sandbergcpu: Unify the serialization code for all of the CPU...
2013-01-07 Andreas Sandbergcpu: Rewrite O3 draining to avoid stopping in microcode
2013-01-07 Andreas Sandbergo3 cpu: Remove unused variables
2013-01-07 Andreas Sandbergcpu: Rename defer_registration->switched_out
2013-01-07 Andreas Sandbergcpu: Correctly call parent on switchOut() and takeOverF...
2013-01-07 Andreas Sandbergcpu: Unify SimpleCPU and O3 CPU serialization code
2013-01-07 Andreas Sandbergcpu: Initialize the O3 pipeline from startup()
2013-01-07 Andreas Sandbergcpu: Check that the memory system is in the correct...
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2013-01-07 Ali Saidicpu: rename the misleading inSyscall to noSquashFromTC
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-08-21 Andreas HanssonClock: Make Tick unsigned and remove UTick
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-03-30 Andreas HanssonCPU: Unify initMemProxies across CPUs and simulation...
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-02 Andreas HanssonCPU: Check that the interrupt controller is created...
2012-03-01 Nilay Vaishx86: Fix switching of CPUs
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-12 Anthony Gutierrezcpu: add separate stats for insts/ops both globally...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
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