projects
/
gem5.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
arch: Get rid of the unused GenericTLB.
[gem5.git]
/
src
/
cpu
/
o3
/
regfile.cc
2019-05-30
Giacomo Gabrielli
cpu-o3: Add support for pinned writes
blob
|
commitdiff
|
raw
2019-01-30
Giacomo Gabrielli
arch,cpu: Add vector predicate registers
blob
|
commitdiff
|
raw
|
diff to current
2017-07-05
Rekai Gonzalez-Alb...
cpu: Added interface for vector reg file
blob
|
commitdiff
|
raw
|
diff to current
2017-07-05
Rekai Gonzalez-Alb...
cpu: Simplify the rename interface and use RegId
blob
|
commitdiff
|
raw
|
diff to current
2017-07-05
Nathanael Premillieu
cpu: Physical register structural + flat indexing
blob
|
commitdiff
|
raw
|
diff to current
2016-11-09
Brandon Potter
style: [patch 1/22] use /r/3648/ to reorganize includes
blob
|
commitdiff
|
raw
|
diff to current
2015-07-28
Nilay Vaish
revert 5af8f40d8f2c
blob
|
commitdiff
|
raw
|
diff to current
2015-07-26
Nilay Vaish
cpu: implements vector registers
blob
|
commitdiff
|
raw
|
diff to current
2013-10-15
Yasuko Eckert
cpu: add a condition-code register class
blob
|
commitdiff
|
raw
|
diff to current
2013-10-15
Steve Reinhardt
cpu/o3: clean up rename map and free list
blob
|
commitdiff
|
raw
|
diff to current