inorder: clear fetchbuffer on traps
[gem5.git] / src / cpu / o3 /
2011-06-11 Korey Sewello3: missing newlines on some dprintfs
2011-06-03 Nathan Binkertscons: rename TraceFlags to DebugFlags
2011-05-23 Geoffrey BlakeO3: Fix offset calculation into storeQueue buffer for...
2011-05-23 Geoffrey BlakeO3: Fix issue w/wbOutstading being decremented multiple...
2011-05-23 Geoffrey BlakeO3: Fix issue with interrupts/faults occuring in the...
2011-05-13 Geoffrey BlakeO3: Fix an issue with a load & branch instruction and...
2011-05-05 Ali SaidiO3: Remove assertion for case that is actually handled...
2011-05-05 Ali SaidiO3: Fix a small corner case with the lsq hazard detecti...
2011-04-21 Nathan Binkertstats: one more name violation
2011-04-20 Nathan Binkertstats: rename stats so they can be used as python expre...
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: fix up code after sorting
2011-04-15 Nathan Binkertincludes: sort all includes
2011-04-04 Ali SaidiARM: Fix checkpoint restoration into O3 CPU and the...
2011-04-04 Ali SaidiARM: Cleanup implementation of ITSTATE and put importan...
2011-04-04 Ali SaidiCPU: Remove references to memory copy operations
2011-04-04 Ali SaidiO3: Tighten memory order violation checking to 16 bytes.
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiO3: Send instruction back to fetch on squash to seed...
2011-03-18 Ali SaidiO3: Cleanup the commitInfo comm struct.
2011-03-18 Ali SaidiMem: Fix issue with dirty block being lost when entire...
2011-03-18 Ali SaidiO3: Fix unaligned stores when cache blocked
2011-02-25 Timothy M. JonesO3CPU: Fix iqCount and lsqCount SMT fetch policies.
2011-02-23 Ali SaidiO3: When a prefetch causes a fault, don't record it...
2011-02-23 Ali SaidiO3: If there is an outstanding table walk don't let...
2011-02-23 Ali SaidiARM: Do something for ISB, DSB, DMB
2011-02-23 Ali SaidiARM: Fix bug that let two table walks occur in parallel.
2011-02-23 Ali SaidiO3: Fix bug when a squash occurs right before TLB miss...
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-18 Korey Sewellm5: merge inorder/release-notes/make_release changes
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-14 Gabe BlackO3: Fetch from the microcode ROM when needed.
2011-02-13 Ali SaidiO3: Fix GCC 4.2.4 complaint
2011-02-12 Giacomo GabrielliO3: Fix pipeline restart when a table walk completes...
2011-02-12 Giacomo GabrielliO3: Enhance data address translation by supporting...
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately.
2011-02-03 Gabe BlackO3: Fix a style bug in O3.
2011-02-02 Gabe BlackX86: Add L1 caches for the TLB walkers.
2011-01-18 Matt HorsnellO3: Fix some variable length instruction issues with...
2011-01-18 Matt HorsnellO3: Don't test misprediction on load instructions until...
2011-01-18 Ali SaidiO3: Keep around the last committed instruction and...
2011-01-18 Ali SaidiO3: Don't try to scoreboard misc registers.
2011-01-18 Matt HorsnellO3: Fix corner cases where multiple squashes/fetch...
2011-01-18 Matt HorsnellO3: Fix mispredicts from non control instructions.
2011-01-18 Matt HorsnellO3: Fixes the way prefetches are handled inside the...
2011-01-18 Ali SaidiO3: Support timing translations for O3 CPU fetch.
2011-01-18 Ali SaidiARM: Add support for moving predicated false dest opera...
2011-01-18 Min Kyu JeongO3: Fixes fetch deadlock when the interrupt clears...
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2011-01-03 Steve ReinhardtMove sched_list.hh and timebuf.hh from src/base to...
2010-12-08 Ali SaidiO3: Allow a store entry to store up to 16 bytes (instea...
2010-12-08 Ali SaidiO3: Support squashing all state after special instruction
2010-12-08 Giacomo GabrielliO3: Make all instructions that write a misc. register...
2010-12-08 Min Kyu JeongO3: Support SWAP and predicated loads/store in ARM.
2010-11-18 Gabe BlackO3: Fix fp destination register flattening, and index...
2010-11-16 Gabe BlackO3: Make O3 support variably lengthed instructions.
2010-11-15 Ali SaidiO3: reset architetural state by calling clear()
2010-11-15 Giacomo GabrielliCPU/ARM: Add SIMD op classes to CPU models and ARM...
2010-11-15 Min Kyu JeongO3: prevent a squash when completeAcc() modifies misc...
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-10-24 Gabe BlackO3: Get rid of a bunch of commented out lines.
2010-10-04 Gabe BlackAlpha: Fix Alpha NumMiscArchRegs constant.
2010-09-20 Gabe BlackCPU: Fix O3 and possible InOrder segfaults in FS.
2010-09-14 Gabe BlackCPU: Get rid of the now unnecessary getInst/setInst...
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-09-10 Nathan Binkertstyle: fix sorting of includes and whitespace in some...
2010-08-26 Min Kyu JeongARM: Fixed register flattening logic (FP_Base_DepTag...
2010-08-23 Gabe BlackISA: Get rid of old, unused utility functions clutterin...
2010-08-23 Min Kyu JeongO3: Skipping mem-order violation check for uncachable...
2010-08-23 Min Kyu JeongARM: Improve printing of uop disassembly.
2010-08-23 Min Kyu JeongCPU: Make Exec trace to print predication result (if...
2010-08-23 Min Kyu JeongARM: mark msr/mrs instructions as SerializeBefore/After
2010-08-23 Min Kyu JeongO3: Handle loads when the destination is the PC.
2010-08-23 Min Kyu JeongARM/O3: store the result of the predicate evaluation...
2010-08-13 Gabe BlackMerge with head.
2010-08-13 Gabe BlackCPU: Add readBytes and writeBytes functions to the...
2010-07-22 Timothy M. JonesLSQ Unit: After deleting part of a split request, set...
2010-07-22 Timothy M. JonesO3CPU: Fix a bug where stores in the cpu where never...
2010-07-22 Timothy M. JonesO3CPU: O3's tick event gets squashed when it is switche...
2010-06-22 Timothy M. JonesO3ThreadContext: When taking over from a previous conte...
2010-02-27 Nathan Binkertcpu_models: get rid of cpu_models.py and move the stuff...
2010-02-12 Timothy M. JonesO3PCU: Split loads and stores that cross cache line...
2010-01-19 Derek Howermerge
2009-11-04 Steve Reinhardto3: get rid of unused physmem pointer
2009-09-26 Steve ReinhardtO3: Add flag to control whether faulting instructions...
2009-09-26 Steve ReinhardtO3: Mark fetch stage as active if it faults.
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to...
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtFix setting of INST_FETCH flag for O3 CPU.
2009-07-25 Korey Sewello3-smt: enforce numThreads parameter for SMT SE mode
2009-07-13 Derek Howermerge
2009-07-09 Gabe BlackGet rid of the unused get(Data|Inst)Asid and (inst...
2009-07-09 Gabe BlackRegisters: Add a registers.hh file as an ISA switched...
2009-07-09 Gabe BlackRegisters: Get rid of the float register width parameter.
2009-07-09 Gabe BlackRegisters: Add an ISA object which replaces the MiscReg...
2009-06-05 Nathan Binkertmove: put predictor includes and cc files into the...
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-05-17 Nathan Binkertincludes: sort includes again
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