style: fix missing spaces in control statements
[gem5.git] / src / cpu / simple / atomic.cc
2016-02-07 Steve Reinhardtstyle: fix missing spaces in control statements
2016-01-18 Steve Reinhardtcpu. arch: add initiateMemRead() to ExecContext interface
2015-09-30 Mitch Hayengacpu,isa,mem: Add per-thread wakeup logic
2015-09-30 Mitch Hayengacpu: Add per-thread monitors
2015-09-30 Mitch Hayengaconfig,cpu: Add SMT support to Atomic and Timing CPUs
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API
2015-04-03 Nikos Nikoleriscpu: fix system total instructions accounting
2015-03-23 Steve Reinhardtmem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW
2015-02-11 Steve Reinhardtmem: restructure Packet cmd initialization a bit more
2015-01-25 Ali Saidisim: Clean up InstRecord
2015-01-20 Nikos Nikoleriscpu: commit probe notification on every microop or...
2014-12-05 Gabe Blackcpu: Only check for PC events on instruction boundaries.
2014-12-02 Andreas Hanssonmem: Add const getters for write packet data
2014-11-14 Andreas Hanssonarm: Fixes based on UBSan and static analysis
2014-11-06 Marc Orrx86 isa: This patch attempts an implementation at mwait.
2014-10-16 Andreas Sandbergcpu: Probe points for basic PMU stats
2014-09-20 Mitch Hayengaalpha,arm,mips,power,x86,cpu,sim: Cleanup activate...
2014-09-20 Dam Sunwoocpu: use probes infrastructure to do simpoint profiling
2014-05-13 Curtis Dunhammem: Refactor assignment of Packet types
2014-01-24 Ali Saidicpu: Add support for instructions that zero cache lines.
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when...
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2014-01-24 Dam Sunwoocpu: remove faulty simpoint basic block inst count...
2013-08-19 Lena Olsoncpu: Accurately count idle cycles for simple cpu
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-04-22 Dam Sunwoocpu: generate SimPoint basic block vector profiles
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-02-15 Andreas Sandbergcpu: Refactor memory system checks
2013-01-07 Andreas Sandbergcpu: Unify the serialization code for all of the CPU...
2013-01-07 Andreas Sandbergcpu: Make sure that a drained atomic CPU isn't executin...
2013-01-07 Andreas Sandbergcpu: Rename defer_registration->switched_out
2013-01-07 Andreas Sandbergcpu: Correctly call parent on switchOut() and takeOverF...
2013-01-07 Andreas Sandbergcpu: Check that the memory system is in the correct...
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-07-09 Andreas HanssonPort: Align port names in C++ and Python
2012-06-05 Anthony Gutierrezcpu: Don't init simple and inorder CPUs if they are...
2012-05-26 Gabe BlackCPU: Merge the predecoder and decoder.
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-04-03 Andreas HanssonAtomic: Remove the physmem_port and access memory directly
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-30 Andreas HanssonCPU: Unify initMemProxies across CPUs and simulation...
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonMEM: Separate queries for snooping and address ranges
2012-01-17 Andreas HanssonCPU: Moving towards a more general port across CPU...
2012-01-17 Andreas HanssonMEM: Add port proxies instead of non-structural ports
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-18 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-11-01 Gabe BlackSE/FS: Expose the same methods on the CPUs in SE and...
2011-07-03 Nilay VaishMerged with Gabe's recent changes.
2011-07-03 Gabe BlackExecContext: Rename the readBytes/writeBytes functions...
2011-07-03 Gabe BlackExecContext: Get rid of the now unused read/write templ...
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Detect and skip udelay() functions in linux kernel.
2011-03-02 Gabe BlackSpelling: Fix the a spelling error by changing mmaped...
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-26 Ali SaidiCPU: Print out traces for faluting inst when the flag...
2010-08-13 Gabe BlackMerge with head.
2010-08-13 Gabe BlackCPU: Add readBytes and writeBytes functions to the...
2010-08-13 Gabe BlackCPU: Tidy up endianness handling for mmapped "IPR"s.
2010-03-27 Korey Sewellm5: merge inorder updates
2010-03-23 Steve Reinhardtcpu: get rid of uncached access "events"
2010-03-23 Steve Reinhardtcpu: fix exec tracing memory corruption bug
2010-01-19 Derek Howermerge
2009-11-18 Brad Beckmannm5: Fixed bug in atomic cpu destructor
2009-11-11 Gabe BlackMerge with the head.
2009-11-11 Gabe BlackMem: Eliminate the NO_FAULT request flag.
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-08-25 Derek Howermerge
2009-08-25 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-23 Gabe BlackMerge with head.
2009-08-23 Gabe BlackAtomic CPU: Respect the NO_ACCESS request flag.
2009-06-05 Nathan Binkerttypes: clean up types, especially signed vs unsigned
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-04-20 Gabe BlackMem: Change isLlsc to isLLSC.
2009-04-19 Gabe BlackCPUs: Make the atomic CPU support locked memory accesses.
2009-04-19 Gabe BlackMemory: Rename LOCKED for load locked store conditional...
2009-04-19 Gabe BlackCPU: If the simple CPU is already idle, just return...
2009-04-09 Nathan Binkerttlb: More fixing of unified TLB
2009-04-09 Gabe Blacktlb: Don't separate the TLB classes into an instruction...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-03-12 Steve Reinhardtcpu: fix minor endian issue with trace output
2009-02-25 Gabe BlackCPU: Don't fetch when executing a macroop.
2009-02-25 Gabe BlackCPU: Implement translateTiming which defers to translat...
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