git.libre-soc.org Git - gem5.git/history - src/cpu/simple/exec

2017-07-05	Rekai Gonzalez-Alb...	arch: ISA parser additions of vector registers	blob \| commitdiff \| raw
2017-07-05	Rekai Gonzalez-Alb...	cpu: Added interface for vector reg file	blob \| commitdiff \| raw \| diff to current
2017-07-05	Rekai Gonzalez-Alb...	cpu: Simplify the rename interface and use RegId	blob \| commitdiff \| raw \| diff to current
2017-07-05	Nathanael Premillieu	arch, cpu: Architectural Register structural indexing	blob \| commitdiff \| raw \| diff to current
2015-07-20	Brandon Potter	syscall_emul: [patch 13/22] add system call retry capab...	blob \| commitdiff \| raw \| diff to current
2016-08-15	Nikos Nikoleris	cpu, arch: fix the type used for the request flags	blob \| commitdiff \| raw \| diff to current
2016-01-18	Steve Reinhardt	cpu. arch: add initiateMemRead() to ExecContext interface	blob \| commitdiff \| raw \| diff to current
2015-10-12	Andreas Hansson	misc: Remove redundant compiler-specific defines	blob \| commitdiff \| raw \| diff to current
2015-09-30	Mitch Hayenga	cpu: Add per-thread monitors	blob \| commitdiff \| raw \| diff to current
2015-09-30	Mitch Hayenga	config,cpu: Add SMT support to Atomic and Timing CPUs	blob \| commitdiff \| raw \| diff to current