trace: reimplement the DTRACE function so it doesn't use a vector
[gem5.git] / src / cpu / simple / timing.cc
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Detect and skip udelay() functions in linux kernel.
2011-03-02 Gabe BlackSpelling: Fix the a spelling error by changing mmaped...
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-12 Ali SaidiSimpleCPU: Fix a case where a DTLB fault redirects...
2011-02-07 Joel HestnessTimingSimpleCPU: split data sender state fix
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-11-15 Ali SaidiCPU: Fix bug when a split transaction is issued to...
2010-11-08 Ali SaidiARM/Alpha/Cpu: Change prefetchs to be more like normal...
2010-10-31 Gabe BlackISA,CPU,etc: Create an ISA defined PC type that abstrac...
2010-09-30 Ali SaidiCPU/Cache: Fix some errors exposed by valgrind
2010-09-14 Gabe BlackFaults: Pass the StaticInst involved, if any, to a...
2010-08-26 Ali SaidiCPU: Print out traces for faluting inst when the flag...
2010-08-13 Gabe BlackMerge with head.
2010-08-13 Gabe BlackCPU: Add readBytes and writeBytes functions to the...
2010-08-13 Joel HestnessTimingSimpleCPU: fix NO_ACCESS memory op handling
2010-03-27 Korey Sewellm5: merge inorder updates
2010-03-23 Steve Reinhardtcpu: get rid of uncached access "events"
2010-03-23 Steve Reinhardtcpu: fix exec tracing memory corruption bug
2010-03-22 Brad BeckmannTimingSimpleCPU: Fixed uncacacheable request read bug
2010-02-12 Timothy M. JonesBaseDynInst: Make the TLB translation timing instead...
2010-01-19 Derek Howermerge
2009-11-11 Gabe BlackMerge with the head.
2009-11-11 Gabe BlackMem: Eliminate the NO_FAULT request flag.
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-06-05 Nathan Binkerttypes: clean up types, especially signed vs unsigned
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-04-20 Gabe BlackMem: Change isLlsc to isLLSC.
2009-04-19 Gabe BlackMemory: Rename LOCKED for load locked store conditional...
2009-04-19 Gabe BlackCPU: If the simple CPU is already idle, just return...
2009-04-09 Nathan Binkerttlb: More fixing of unified TLB
2009-04-09 Gabe Blacktlb: Don't separate the TLB classes into an instruction...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-03-12 Steve Reinhardtcpu: fix minor endian issue with trace output
2009-02-25 Gabe BlackCPU: Don't fetch when executing a macroop.
2009-02-25 Gabe BlackCPU: Implement translateTiming which defers to translat...
2009-02-25 Gabe BlackISA: Replace the translate functions in the TLBs with...
2009-02-25 Gabe BlackCPU: Get rid of translate... functions from various...
2008-11-14 Gabe BlackCPU: Refactor read/write in the simple timing CPU.
2008-11-10 Gabe BlackCPU: Make unaligned accesses work in the timing simple...
2008-11-10 Gabe BlackX86: Make the timing simple CPU handle variable length...
2008-11-03 Lisa HsuAdd in Context IDs to the simulator. From now on,...
2008-11-03 Lisa Hsumake BaseCPU the provider of _cpuId, and cpuId() instea...
2008-10-27 Clint SmullenCPU: The API change to EventWrapper did not get propag...
2008-10-13 Gabe BlackX86: Don't fetch in the simple CPU if you're in the...
2008-10-09 Nathan Binkerteventq: convert all usage of events to use the new...
2008-08-11 Nathan Binkertparams: Convert the CPU objects to use the auto generat...
2008-07-15 Steve ReinhardtUse ReadResp instead of LoadLockedResp for LoadLockedRe...
2008-07-01 Ali SaidiMake the cached virtPort have a thread context so it...
2008-07-01 Ali SaidiAfter a checkpoint (and thus a stats reset), the not_id...
2008-06-12 Gabe BlackCPU: Make the simple cpu trace data for loads/stores.
2008-02-14 Ali SaidiCPU: move the PC Events code to a place where the code...
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-06 Stephen HinesMake the Event::description() a const function
2008-02-06 Stephen HinesAdd base ARM code to M5
2008-01-02 Steve ReinhardtAdditional comments and helper functions for PrintReq.
2007-12-16 Ali SaidiCPU: Update where the simple cpus read their cpu id...
2007-11-08 Ali SaidiTimingSimpleCPU: Add some DPRINTFs when the cpu suspend...
2007-10-31 Steve ReinhardtMerge in bus DPRINTF changes.
2007-10-22 Gabe BlackMerge with head.
2007-10-22 Gabe BlackCPU: Add functions to the "ExecContext"s that translate...
2007-10-19 Gabe BlackMerge with head.
2007-10-18 Ali SaidiCPU: Use the ThreadContext cpu id instead of the params...
2007-10-03 Gabe BlackMerge with head.
2007-10-01 Ali SaidiCPU: fix sparc_fs booting with SimpleTimingCPU.
2007-09-28 Ali SaidiUpdate stats for quiesced cycles
2007-09-28 Ali SaidiRename cycles() function to ticks()
2007-09-28 Ali SaidiUpdate statistics to use cycles properly instead of...
2007-08-28 Gabe BlackMerge with head.
2007-08-27 Gabe BlackMerge with head
2007-08-27 Gabe BlackSimple CPU: Don't trace instructions that fault. Otherw...
2007-08-27 Gabe BlackSimple CPU: Make sure only instructions which complete...
2007-08-27 Gabe BlackAddress Translation: Make SE mode use an actual TLB...
2007-08-24 Ali SaidiMem: Make errors in the memory system be responses...
2007-08-05 Gabe BlackMerge with head.
2007-08-03 Steve Reinhardtmerge from head
2007-08-01 Nathan Binkertmerge: mips fix to getArgument
2007-08-01 Gabe BlackMerge with head.
2007-08-01 Gabe BlackMerge with head.
2007-07-31 Steve ReinhardtMerge from head.
2007-07-29 Steve ReinhardtMerge Gabe's changes from head.
2007-07-29 Gabe BlackMerge ... head. style.py was also missing an argument...
2007-07-29 Nathan Binkertmerge: style.py fix
2007-07-29 Gabe BlackMerge with head.
2007-07-29 Gabe BlackTurn the instruction tracing code into pluggable sim...
2007-07-29 Nathan Binkertmerge whitespace fixes
2007-07-29 Nathan Binkertmerge whitespace changes
2007-07-27 Nathan BinkertMerge python and x86 changes with cache branch
2007-07-24 Gabe BlackMerge with head.
2007-07-24 Nathan BinkertMajor changes to how SimObjects are created and initial...
2007-07-22 Steve ReinhardtMerge from head.
2007-07-22 Steve ReinhardtMerge more changes in from head.
2007-07-16 Steve ReinhardtMerge from head.
2007-07-14 Steve ReinhardtMerge from head.
2007-07-14 Steve ReinhardtMerge of DPRINTF fixes from head.
2007-07-14 Steve ReinhardtMerge in .hgignore from head.
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