2017-07-12 |
Sean Wilson | cpu: Refactor some Event subclasses to lambdas |
tree | commitdiff |
2017-07-05 |
Rekai Gonzalez-Alb... | arch: ISA parser additions of vector registers |
tree | commitdiff |
2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Added interface for vector reg file |
tree | commitdiff |
2017-07-05 |
Rekai Gonzalez-Alb... | cpu: Simplify the rename interface and use RegId |
tree | commitdiff |
2017-07-05 |
Nathanael Premillieu | arch, cpu: Architectural Register structural indexing |
tree | commitdiff |
2017-06-20 |
Sean Wilson | cpu, gpu-compute: Replace EventWrapper use with EventFu... |
tree | commitdiff |
2015-07-20 |
Brandon Potter | syscall_emul: [patch 13/22] add system call retry capab... |
tree | commitdiff |
2016-11-09 |
Brandon Potter | style: [patch 1/22] use /r/3648/ to reorganize includes |
tree | commitdiff |
2016-08-15 |
Nikos Nikoleris | cpu, arch: fix the type used for the request flags |
tree | commitdiff |
2016-06-06 |
David Guillen Fandos | pwr: Low-power idle power state for idle CPUs |
tree | commitdiff |
2016-04-07 |
Mitch Hayenga | mem: Remove threadId from memory request class |
tree | commitdiff |
2016-04-06 |
Andreas Sandberg | Revert power patch sets with unexpected interactions |
tree | commitdiff |
2016-04-05 |
Mitch Hayenga | mem: Remove threadId from memory request class |
tree | commitdiff |
2014-12-09 |
Akash Bagdia | power: Low-power idle power state for idle CPUs |
tree | commitdiff |
2015-11-27 |
Andreas Sandberg | base: Add support for changing output directories |
tree | commitdiff |
2015-07-19 |
Krishnendra Nathella | cpu: Fix LLSC atomic CPU wakeup |
tree | commitdiff |
2016-02-10 |
Andreas Hansson | mem: Deduce if cache should forward snoops |
tree | commitdiff |
2016-02-07 |
Steve Reinhardt | style: fix missing spaces in control statements |
tree | commitdiff |
2016-02-07 |
Steve Reinhardt | style: remove trailing whitespace |
tree | commitdiff |
2016-01-18 |
Steve Reinhardt | cpu. arch: add initiateMemRead() to ExecContext interface |
tree | commitdiff |
2015-10-12 |
Andreas Hansson | misc: Add explicit overrides and fix other clang >... |
tree | commitdiff |
2015-10-12 |
Andreas Hansson | misc: Remove redundant compiler-specific defines |
tree | commitdiff |
2015-09-30 |
Mitch Hayenga | cpu,isa,mem: Add per-thread wakeup logic |
tree | commitdiff |
2015-09-30 |
Mitch Hayenga | isa,cpu: Add support for FS SMT Interrupts |
tree | commitdiff |
2015-09-30 |
Mitch Hayenga | cpu: Add per-thread monitors |
tree | commitdiff |
2015-09-30 |
Mitch Hayenga | config,cpu: Add SMT support to Atomic and Timing CPUs |
tree | commitdiff |
2015-07-28 |
Nilay Vaish | revert 5af8f40d8f2c |
tree | commitdiff |
2015-07-26 |
Nilay Vaish | cpu: implements vector registers |
tree | commitdiff |
2015-07-07 |
Andreas Sandberg | sim: Refactor and simplify the drain API |
tree | commitdiff |
2015-07-07 |
Andreas Sandberg | sim: Refactor the serialization base class |
tree | commitdiff |
2015-04-13 |
Dibakar Gope | cpu: re-organizes the branch predictor structure. |
tree | commitdiff |
2015-04-03 |
Nikos Nikoleris | cpu: fix system total instructions accounting |
tree | commitdiff |
2015-03-23 |
Steve Reinhardt | mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW |
tree | commitdiff |
2015-02-11 |
Steve Reinhardt | mem: restructure Packet cmd initialization a bit more |
tree | commitdiff |
2015-03-02 |
Andreas Hansson | mem: Split port retry for all different packet classes |
tree | commitdiff |
2015-02-16 |
Andreas Hansson | arch: Make readMiscRegNoEffect const throughout |
tree | commitdiff |
2015-02-03 |
Andreas Hansson | cpu: Ensure timing CPU sinks response before sending... |
tree | commitdiff |
2015-01-25 |
Ali Saidi | sim: Clean up InstRecord |
tree | commitdiff |
2015-01-25 |
Ali Saidi | cpu: Remove all notion that we know when the cpu is... |
tree | commitdiff |
2015-01-22 |
Andreas Hansson | mem: Clean up Request initialisation |
tree | commitdiff |
2015-01-20 |
Nikos Nikoleris | cpu: commit probe notification on every microop or... |
tree | commitdiff |
2014-12-05 |
Gabe Black | cpu: Only check for PC events on instruction boundaries. |
tree | commitdiff |
2014-12-02 |
Andreas Hansson | mem: Assume all dynamic packet data is array allocated |
tree | commitdiff |
2014-12-02 |
Andreas Hansson | mem: Add const getters for write packet data |
tree | commitdiff |
2014-11-14 |
Andreas Hansson | arm: Fixes based on UBSan and static analysis |
tree | commitdiff |
2014-11-12 |
Ali Saidi | arm: Fix timing wakeup with LLSC |
tree | commitdiff |
2014-11-06 |
Marc Orr | x86 isa: This patch attempts an implementation at mwait. |
tree | commitdiff |
2014-10-16 |
Andreas Sandberg | cpu: Probe points for basic PMU stats |
tree | commitdiff |
2014-09-27 |
Andreas Hansson | arch: Use const StaticInstPtr references where possible |
tree | commitdiff |
2014-09-20 |
Mitch Hayenga | cpu: Remove unused deallocateContext calls |
tree | commitdiff |
2014-09-20 |
Mitch Hayenga | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate... |
tree | commitdiff |
2014-09-20 |
Dam Sunwoo | cpu: use probes infrastructure to do simpoint profiling |
tree | commitdiff |
2014-09-19 |
Andreas Hansson | arch: Pass faults by const reference where possible |
tree | commitdiff |
2014-05-13 |
Curtis Dunham | mem: Refactor assignment of Packet types |
tree | commitdiff |
2014-09-03 |
Andreas Sandberg | arch, cpu: Factor out the ExecContext into a proper... |
tree | commitdiff |
2014-05-09 |
Curtis Dunham | cpu: add more instruction mix statistics |
tree | commitdiff |
2014-02-09 |
Andreas Sandberg | cpu: simple: Add support for using branch predictors |
tree | commitdiff |
2014-01-24 |
Ali Saidi | cpu: Add support for instructions that zero cache lines. |
tree | commitdiff |
2014-01-24 |
Ali Saidi | cpu: Add CPU support for generatig wake up events when... |
tree | commitdiff |
2014-01-24 |
Dam Sunwoo | mem: per-thread cache occupancy and per-block ages |
tree | commitdiff |
2014-01-24 |
Matt Horsnell | mem: track per-request latencies and access depths... |
tree | commitdiff |
2014-01-24 |
Dam Sunwoo | cpu: remove faulty simpoint basic block inst count... |
tree | commitdiff |
2013-10-15 |
Yasuko Eckert | cpu: add a condition-code register class |
tree | commitdiff |
2013-10-15 |
Steve Reinhardt | cpu: rename *_DepTag constants to *_Reg_Base |
tree | commitdiff |
2013-08-20 |
Andreas Hansson | cpu: Fix timing CPU isDrained comment formatting |
tree | commitdiff |
2013-08-19 |
Lena Olson | cpu: Accurately count idle cycles for simple cpu |
tree | commitdiff |
2013-08-19 |
Andreas Hansson | cpu: Fix timing CPU drain check |
tree | commitdiff |
2013-07-18 |
Andreas Hansson | mem: Set the cache line size on a system level |
tree | commitdiff |
2013-05-30 |
Andreas Hansson | cpu: Make hash struct instead of class to please clang |
tree | commitdiff |
2013-04-22 |
Dam Sunwoo | sim: separate nextCycle() and clockEdge() in clockedObjects |
tree | commitdiff |
2013-04-22 |
Dam Sunwoo | cpu: generate SimPoint basic block vector profiles |
tree | commitdiff |
2013-03-26 |
Andreas Hansson | cpu: Remove CpuPort and use MasterPort in the CPU classes |
tree | commitdiff |
2013-02-15 |
Andreas Sandberg | sim: Add a system-global option to bypass caches |
tree | commitdiff |
2013-02-15 |
Andreas Sandberg | cpu: Refactor memory system checks |
tree | commitdiff |
2013-02-15 |
Andreas Sandberg | cpu: Add CPU metadata om the Python classes |
tree | commitdiff |
2013-01-13 |
Nilay Vaish | base simple cpu: removes commented out code about cache ops |
tree | commitdiff |
2013-01-13 |
Nilay Vaish | x86: Changes to decoder, corrects 9376 |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | cpu: Unify the serialization code for all of the CPU... |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | cpu: Make sure that a drained atomic CPU isn't executin... |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | cpu: Make sure that a drained timing CPU isn't executin... |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | cpu: Rename defer_registration->switched_out |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | cpu: Correctly call parent on switchOut() and takeOverF... |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | cpu: Check that the memory system is in the correct... |
tree | commitdiff |
2013-01-07 |
Andreas Sandberg | arch: Make the ISA class inherit from SimObject |
tree | commitdiff |
2013-01-05 |
Gabe Black | Decoder: Remove the thread context get/set from the... |
tree | commitdiff |
2012-11-02 |
Andreas Sandberg | sim: Move the draining interface into a separate base... |
tree | commitdiff |
2012-11-02 |
Andreas Sandberg | sim: Include object header files in SWIG interfaces |
tree | commitdiff |
2012-09-25 |
Ali Saidi | ARM: Squash outstanding walks when instructions are... |
tree | commitdiff |
2012-09-19 |
Andreas Hansson | AddrRange: Transition from Range<T> to AddrRange |
tree | commitdiff |
2012-08-28 |
Andreas Hansson | Clock: Add a Cycles wrapper class and use where applicable |
tree | commitdiff |
2012-08-28 |
Andreas Hansson | Clock: Rework clocks to avoid tick-to-cycle transformations |
tree | commitdiff |
2012-08-22 |
Andreas Hansson | Packet: Remove NACKs from packet and its use in endpoints |
tree | commitdiff |
2012-08-15 |
Anthony Gutierrez | O3,ARM: fix some problems with drain/switchout function... |
tree | commitdiff |
2012-07-09 |
Andreas Hansson | Port: Align port names in C++ and Python |
tree | commitdiff |
2012-07-09 |
Andreas Hansson | Port: Move retry from port base class to Master/SlavePort |
tree | commitdiff |
2012-06-08 |
Andreas Hansson | Timing CPU: Remove a redundant port pointer |
tree | commitdiff |
2012-06-05 |
Anthony Gutierrez | cpu: Don't init simple and inorder CPUs if they are... |
tree | commitdiff |
2012-05-26 |
Gabe Black | CPU: Merge the predecoder and decoder. |
tree | commitdiff |
2012-05-25 |
Gabe Black | Decode: Make the Decoder class defined per ISA. |
tree | commitdiff |
2012-05-01 |
Andreas Hansson | MEM: Separate requests and responses for timing accesses |
tree | commitdiff |
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