projects / gem5.git / history
? search:
summary | shortlog | log | commit | commitdiff | tree
first ⋅ prev ⋅ next
pwr: Adds logic to enter power gating for the cpu model
[gem5.git] / src / cpu / simple /
2017-11-20 Anouk Van Laerpwr: Adds logic to enter power gating for the cpu model tree | commitdiff
2017-07-12 Sean Wilsoncpu: Refactor some Event subclasses to lambdas tree | commitdiff
2017-07-05 Rekai Gonzalez-Alb... arch: ISA parser additions of vector registers tree | commitdiff
2017-07-05 Rekai Gonzalez-Alb... cpu: Added interface for vector reg file tree | commitdiff
2017-07-05 Rekai Gonzalez-Alb... cpu: Simplify the rename interface and use RegId tree | commitdiff
2017-07-05 Nathanael Premillieuarch, cpu: Architectural Register structural indexing tree | commitdiff
2017-06-20 Sean Wilsoncpu, gpu-compute: Replace EventWrapper use with EventFu... tree | commitdiff
2015-07-20 Brandon Pottersyscall_emul: [patch 13/22] add system call retry capab... tree | commitdiff
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes tree | commitdiff
2016-08-15 Nikos Nikoleriscpu, arch: fix the type used for the request flags tree | commitdiff
2016-06-06 David Guillen Fandospwr: Low-power idle power state for idle CPUs tree | commitdiff
2016-04-07 Mitch Hayengamem: Remove threadId from memory request class tree | commitdiff
2016-04-06 Andreas SandbergRevert power patch sets with unexpected interactions tree | commitdiff
2016-04-05 Mitch Hayengamem: Remove threadId from memory request class tree | commitdiff
2014-12-09 Akash Bagdiapower: Low-power idle power state for idle CPUs tree | commitdiff
2015-11-27 Andreas Sandbergbase: Add support for changing output directories tree | commitdiff
2015-07-19 Krishnendra Nathellacpu: Fix LLSC atomic CPU wakeup tree | commitdiff
2016-02-10 Andreas Hanssonmem: Deduce if cache should forward snoops tree | commitdiff
2016-02-07 Steve Reinhardtstyle: fix missing spaces in control statements tree | commitdiff
2016-02-07 Steve Reinhardtstyle: remove trailing whitespace tree | commitdiff
2016-01-18 Steve Reinhardtcpu. arch: add initiateMemRead() to ExecContext interface tree | commitdiff
2015-10-12 Andreas Hanssonmisc: Add explicit overrides and fix other clang >... tree | commitdiff
2015-10-12 Andreas Hanssonmisc: Remove redundant compiler-specific defines tree | commitdiff
2015-09-30 Mitch Hayengacpu,isa,mem: Add per-thread wakeup logic tree | commitdiff
2015-09-30 Mitch Hayengaisa,cpu: Add support for FS SMT Interrupts tree | commitdiff
2015-09-30 Mitch Hayengacpu: Add per-thread monitors tree | commitdiff
2015-09-30 Mitch Hayengaconfig,cpu: Add SMT support to Atomic and Timing CPUs tree | commitdiff
2015-07-28 Nilay Vaishrevert 5af8f40d8f2c tree | commitdiff
2015-07-26 Nilay Vaishcpu: implements vector registers tree | commitdiff
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API tree | commitdiff
2015-07-07 Andreas Sandbergsim: Refactor the serialization base class tree | commitdiff
2015-04-13 Dibakar Gopecpu: re-organizes the branch predictor structure. tree | commitdiff
2015-04-03 Nikos Nikoleriscpu: fix system total instructions accounting tree | commitdiff
2015-03-23 Steve Reinhardtmem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW tree | commitdiff
2015-02-11 Steve Reinhardtmem: restructure Packet cmd initialization a bit more tree | commitdiff
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes tree | commitdiff
2015-02-16 Andreas Hanssonarch: Make readMiscRegNoEffect const throughout tree | commitdiff
2015-02-03 Andreas Hanssoncpu: Ensure timing CPU sinks response before sending... tree | commitdiff
2015-01-25 Ali Saidisim: Clean up InstRecord tree | commitdiff
2015-01-25 Ali Saidicpu: Remove all notion that we know when the cpu is... tree | commitdiff
2015-01-22 Andreas Hanssonmem: Clean up Request initialisation tree | commitdiff
2015-01-20 Nikos Nikoleriscpu: commit probe notification on every microop or... tree | commitdiff
2014-12-05 Gabe Blackcpu: Only check for PC events on instruction boundaries. tree | commitdiff
2014-12-02 Andreas Hanssonmem: Assume all dynamic packet data is array allocated tree | commitdiff
2014-12-02 Andreas Hanssonmem: Add const getters for write packet data tree | commitdiff
2014-11-14 Andreas Hanssonarm: Fixes based on UBSan and static analysis tree | commitdiff
2014-11-12 Ali Saidiarm: Fix timing wakeup with LLSC tree | commitdiff
2014-11-06 Marc Orrx86 isa: This patch attempts an implementation at mwait. tree | commitdiff
2014-10-16 Andreas Sandbergcpu: Probe points for basic PMU stats tree | commitdiff
2014-09-27 Andreas Hanssonarch: Use const StaticInstPtr references where possible tree | commitdiff
2014-09-20 Mitch Hayengacpu: Remove unused deallocateContext calls tree | commitdiff
2014-09-20 Mitch Hayengaalpha,arm,mips,power,x86,cpu,sim: Cleanup activate... tree | commitdiff
2014-09-20 Dam Sunwoocpu: use probes infrastructure to do simpoint profiling tree | commitdiff
2014-09-19 Andreas Hanssonarch: Pass faults by const reference where possible tree | commitdiff
2014-05-13 Curtis Dunhammem: Refactor assignment of Packet types tree | commitdiff
2014-09-03 Andreas Sandbergarch, cpu: Factor out the ExecContext into a proper... tree | commitdiff
2014-05-09 Curtis Dunhamcpu: add more instruction mix statistics tree | commitdiff
2014-02-09 Andreas Sandbergcpu: simple: Add support for using branch predictors tree | commitdiff
2014-01-24 Ali Saidicpu: Add support for instructions that zero cache lines. tree | commitdiff
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when... tree | commitdiff
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages tree | commitdiff
2014-01-24 Matt Horsnellmem: track per-request latencies and access depths... tree | commitdiff
2014-01-24 Dam Sunwoocpu: remove faulty simpoint basic block inst count... tree | commitdiff
2013-10-15 Yasuko Eckertcpu: add a condition-code register class tree | commitdiff
2013-10-15 Steve Reinhardtcpu: rename *_DepTag constants to *_Reg_Base tree | commitdiff
2013-08-20 Andreas Hanssoncpu: Fix timing CPU isDrained comment formatting tree | commitdiff
2013-08-19 Lena Olsoncpu: Accurately count idle cycles for simple cpu tree | commitdiff
2013-08-19 Andreas Hanssoncpu: Fix timing CPU drain check tree | commitdiff
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level tree | commitdiff
2013-05-30 Andreas Hanssoncpu: Make hash struct instead of class to please clang tree | commitdiff
2013-04-22 Dam Sunwoosim: separate nextCycle() and clockEdge() in clockedObjects tree | commitdiff
2013-04-22 Dam Sunwoocpu: generate SimPoint basic block vector profiles tree | commitdiff
2013-03-26 Andreas Hanssoncpu: Remove CpuPort and use MasterPort in the CPU classes tree | commitdiff
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches tree | commitdiff
2013-02-15 Andreas Sandbergcpu: Refactor memory system checks tree | commitdiff
2013-02-15 Andreas Sandbergcpu: Add CPU metadata om the Python classes tree | commitdiff
2013-01-13 Nilay Vaishbase simple cpu: removes commented out code about cache ops tree | commitdiff
2013-01-13 Nilay Vaishx86: Changes to decoder, corrects 9376 tree | commitdiff
2013-01-07 Andreas Sandbergcpu: Unify the serialization code for all of the CPU... tree | commitdiff
2013-01-07 Andreas Sandbergcpu: Make sure that a drained atomic CPU isn't executin... tree | commitdiff
2013-01-07 Andreas Sandbergcpu: Make sure that a drained timing CPU isn't executin... tree | commitdiff
2013-01-07 Andreas Sandbergcpu: Rename defer_registration->switched_out tree | commitdiff
2013-01-07 Andreas Sandbergcpu: Correctly call parent on switchOut() and takeOverF... tree | commitdiff
2013-01-07 Andreas Sandbergcpu: Check that the memory system is in the correct... tree | commitdiff
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject tree | commitdiff
2013-01-05 Gabe BlackDecoder: Remove the thread context get/set from the... tree | commitdiff
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base... tree | commitdiff
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces tree | commitdiff
2012-09-25 Ali SaidiARM: Squash outstanding walks when instructions are... tree | commitdiff
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange tree | commitdiff
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable tree | commitdiff
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations tree | commitdiff
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints tree | commitdiff
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function... tree | commitdiff
2012-07-09 Andreas HanssonPort: Align port names in C++ and Python tree | commitdiff
2012-07-09 Andreas HanssonPort: Move retry from port base class to Master/SlavePort tree | commitdiff
2012-06-08 Andreas HanssonTiming CPU: Remove a redundant port pointer tree | commitdiff
2012-06-05 Anthony Gutierrezcpu: Don't init simple and inorder CPUs if they are... tree | commitdiff
2012-05-26 Gabe BlackCPU: Merge the predecoder and decoder. tree | commitdiff
2012-05-25 Gabe BlackDecode: Make the Decoder class defined per ISA. tree | commitdiff
next