cpu: implement a bi-mode branch predictor
[gem5.git] / src / cpu / simple /
2014-05-09 Curtis Dunhamcpu: add more instruction mix statistics
2014-02-09 Andreas Sandbergcpu: simple: Add support for using branch predictors
2014-01-24 Ali Saidicpu: Add support for instructions that zero cache lines.
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when...
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2014-01-24 Matt Horsnellmem: track per-request latencies and access depths...
2014-01-24 Dam Sunwoocpu: remove faulty simpoint basic block inst count...
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
2013-10-15 Steve Reinhardtcpu: rename *_DepTag constants to *_Reg_Base
2013-08-20 Andreas Hanssoncpu: Fix timing CPU isDrained comment formatting
2013-08-19 Lena Olsoncpu: Accurately count idle cycles for simple cpu
2013-08-19 Andreas Hanssoncpu: Fix timing CPU drain check
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level
2013-05-30 Andreas Hanssoncpu: Make hash struct instead of class to please clang
2013-04-22 Dam Sunwoosim: separate nextCycle() and clockEdge() in clockedObjects
2013-04-22 Dam Sunwoocpu: generate SimPoint basic block vector profiles
2013-03-26 Andreas Hanssoncpu: Remove CpuPort and use MasterPort in the CPU classes
2013-02-15 Andreas Sandbergsim: Add a system-global option to bypass caches
2013-02-15 Andreas Sandbergcpu: Refactor memory system checks
2013-02-15 Andreas Sandbergcpu: Add CPU metadata om the Python classes
2013-01-13 Nilay Vaishbase simple cpu: removes commented out code about cache ops
2013-01-13 Nilay Vaishx86: Changes to decoder, corrects 9376
2013-01-07 Andreas Sandbergcpu: Unify the serialization code for all of the CPU...
2013-01-07 Andreas Sandbergcpu: Make sure that a drained atomic CPU isn't executin...
2013-01-07 Andreas Sandbergcpu: Make sure that a drained timing CPU isn't executin...
2013-01-07 Andreas Sandbergcpu: Rename defer_registration->switched_out
2013-01-07 Andreas Sandbergcpu: Correctly call parent on switchOut() and takeOverF...
2013-01-07 Andreas Sandbergcpu: Check that the memory system is in the correct...
2013-01-07 Andreas Sandbergarch: Make the ISA class inherit from SimObject
2013-01-05 Gabe BlackDecoder: Remove the thread context get/set from the...
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-09-25 Ali SaidiARM: Squash outstanding walks when instructions are...
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-07-09 Andreas HanssonPort: Align port names in C++ and Python
2012-07-09 Andreas HanssonPort: Move retry from port base class to Master/SlavePort
2012-06-08 Andreas HanssonTiming CPU: Remove a redundant port pointer
2012-06-05 Anthony Gutierrezcpu: Don't init simple and inorder CPUs if they are...
2012-05-26 Gabe BlackCPU: Merge the predecoder and decoder.
2012-05-25 Gabe BlackDecode: Make the Decoder class defined per ISA.
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-15 Gabe BlackCPU: Tidy up some formatting and a DPRINTF in the simpl...
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-04-03 Andreas HanssonAtomic: Remove the physmem_port and access memory directly
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-30 Andreas HanssonCPU: Unify initMemProxies across CPUs and simulation...
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-12 Anthony Gutierrezcpu: add separate stats for insts/ops both globally...
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-10 Gabe BlackSE/FS: Record the system pointer all the time for the...
2012-02-07 Gabe BlackFaults: Turn off arch/faults.hh
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Geoffrey BlakeCheckerCPU: Re-factor CheckerCPU to be compatible with...
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-29 Gabe BlackImplement Ali's review feedback.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 Andreas HanssonMEM: Separate queries for snooping and address ranges
2012-01-17 Andreas HanssonMEM: Simplify ports by removing EventManager
2012-01-17 Andreas HanssonCPU: Moving towards a more general port across CPU...
2012-01-17 Andreas HanssonMEM: Add port proxies instead of non-structural ports
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-18 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in the CPU directory.
2011-11-01 Gabe BlackSE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
2011-11-01 Gabe BlackSE/FS: Expose the same methods on the CPUs in SE and...
2011-09-19 Gabe BlackSyscall: Make the syscall function available in both...
2011-09-09 Gabe BlackDecode: Pull instruction decoding out of the StaticInst...
2011-08-07 Gabe BlackTranslation: Use a pointer type as the template argument.
2011-07-03 Nilay VaishMerged with Gabe's recent changes.
2011-07-03 Gabe BlackExecContext: Rename the readBytes/writeBytes functions...
2011-07-03 Gabe BlackExecContext: Get rid of the now unused read/write templ...
2011-06-03 Nathan Binkertscons: rename TraceFlags to DebugFlags
2011-05-05 Ali SaidiCPU: Add some useful debug message to the timing simple...
2011-05-05 Ali SaidiCPU: Fix a case where timing simple cpu faults can...
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Detect and skip udelay() functions in linux kernel.
2011-03-02 Gabe BlackSpelling: Fix the a spelling error by changing mmaped...
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-12 Ali SaidiSimpleCPU: Fix a case where a DTLB fault redirects...
2011-02-12 Giacomo GabrielliO3: Enhance data address translation by supporting...
2011-02-07 Joel HestnessTimingSimpleCPU: split data sender state fix
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately.
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-12-08 Giacomo GabrielliO3: Make all instructions that write a misc. register...
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