inorder: stall signal handling
[gem5.git] / src / cpu /
2010-06-23 Korey Sewellinorder: stall signal handling
2010-06-23 Korey Sewellinorder: tick scheduling
2010-06-22 Timothy M. JonesO3ThreadContext: When taking over from a previous conte...
2010-06-15 Nathan Binkertstats: get rid of the never-really-used event stuff
2010-06-11 Nathan Binkertruby: get rid of the Map class
2010-06-11 Nathan Binkertruby: get rid of Vector and use STL
2010-06-03 Steve ReinhardtMinor remote GDB cleanup.
2010-06-02 Gabe BlackARM: Implement support for the IT instruction and the...
2010-06-02 Ali SaidiARM: Implement the ARM TLB/Tablewalker. Needs performan...
2010-06-02 Ali SaidiARM: Implement ARM CPU interrupts
2010-06-02 Ali SaidiARM: Move PC mode bits around so they can be used for...
2010-06-02 Gabe BlackSimple CPU: Make the FloatRegs trace flag do something.
2010-06-02 Ali SaidiCPU: Reset fetch offset after a exception
2010-06-02 Gabe BlackARM: Make the predecoder handle Thumb instructions.
2010-05-14 Ali SaidiAutomated merge with ssh://m5sim.org//repo/m5
2010-05-14 Maximilien BreugheBPRED: Fixed the treshold-bug in the tournament predictor.
2010-04-15 Nathan Binkerttick: rename Clock namespace to SimClock
2010-04-11 Korey Sewellinorder: timing for inst forwarding
2010-04-02 Nathan Binkertruby: get rid of gems_common/util.hh and .cc and use...
2010-04-02 Nathan Binkertruby: get "using namespace" out of headers
2010-03-30 Nathan Binkertstyle: cleanup the Ruby Tester
2010-03-27 Korey Sewellm5: merge inorder updates
2010-03-27 Korey Sewellinorder: write-hints bug fix
2010-03-25 Timothy M. JonesCPU: Added comments to address translation classes.
2010-03-23 Steve Reinhardtcpu: get rid of uncached access "events"
2010-03-23 Steve Reinhardtcpu: fix exec tracing memory corruption bug
2010-03-22 Korey Sewellinorder: import name for addtl. bpred stats
2010-03-22 Maximilien Breugheinorder: fix squash bug in branch predictor
2010-03-22 Korey Sewellinorder: fix address list bug
2010-03-22 Brad BeckmannTimingSimpleCPU: Fixed uncacacheable request read bug
2010-03-11 Nathan Binkertruby: get rid of std-includes.hh
2010-02-27 Nathan Binkertcpu_models: get rid of cpu_models.py and move the stuff...
2010-02-20 Timothy M. JonesBaseDynInst: Preserve the faults returned from read...
2010-02-12 Timothy M. JonesO3PCU: Split loads and stores that cross cache line...
2010-02-12 Timothy M. JonesBaseDynInst: Make the TLB translation timing instead...
2010-02-01 Brad Beckmannmerge
2010-01-31 Korey Sewellinorder: double delete inst bug
2010-01-31 Korey Sewellinorder: inst count mgmt
2010-01-31 Korey Sewellinorder: implement split stores
2010-01-31 Korey Sewellinorder: implement split loads
2010-01-31 Korey Sewellinorder: add activity stats
2010-01-31 Korey Sewellinorder: object cleanup in destructors
2010-01-31 Korey Sewellinorder: user per-thread dummy insts/reqs
2010-01-31 Korey Sewellinorder: add execution unit stats
2010-01-31 Korey Sewellinorder: recvRetry bug fix
2010-01-31 Korey Sewellinorder-stats: add prereq to basic stat
2010-01-31 Korey Sewellinorder: ctxt switch stats
2010-01-31 Korey Sewellinorder: pipeline stage stats
2010-01-31 Korey Sewellinorder: enforce stage bandwidth
2010-01-31 Korey Sewellinorder: set thread status'
2010-01-31 Korey Sewellinorder: add/remove halt/deallocate context respectively
2010-01-31 Korey Sewellinorder: track last branch committed
2010-01-31 Korey Sewellinorder: add updatePC event to resPool
2010-01-31 Korey Sewellinorder: ready thread wakeup
2010-01-31 Korey Sewellinorder: add threadmodel flag
2010-01-31 Korey Sewellinorder: mem. mgmt. update
2010-01-31 Korey Sewellinorder: suspend in respool
2010-01-31 Korey Sewellinorder: fetch thread bug
2010-01-31 Korey Sewellinorder: ready/suspend status fns
2010-01-31 Korey Sewellinorder-cleanup: remove unused thread functions
2010-01-31 Korey Sewellinorder: activate thread on cache miss
2010-01-31 Korey Sewellinorder: add event priority offset
2010-01-31 Korey Sewellinorder: squash on memory stall
2010-01-31 Korey Sewellinorder: add insts to cpu event
2010-01-31 Korey Sewellinorder: switch out buffer
2010-01-31 Korey Sewellinorder: dont allow early loads
2010-01-31 Korey Sewellconfigs/inorder: add options for switch-on-miss to...
2010-01-31 Korey Sewellinorder: init internal debug cpu counters
2010-01-30 Brad Beckmannruby: added the GEMS ruby tester
2010-01-22 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2010-01-19 Derek Howermerge
2010-01-18 Lisa HsuAutomated merge with ssh://hsul@localhost:4444//repo/m5
2010-01-12 Lisa Hsusince totalInstructions() is impl'ed by all the cpus...
2009-11-18 Brad Beckmannm5: Fixed bug in atomic cpu destructor
2009-11-11 Gabe BlackMerge with the head.
2009-11-11 Gabe BlackMem: Eliminate the NO_FAULT request flag.
2009-11-05 Nathan Binkertbuild: fix compile problems pointed out by gcc 4.4
2009-11-04 Steve Reinhardto3: get rid of unused physmem pointer
2009-10-27 Timothy M. JonesPOWER: Add support for the Power ISA
2009-10-18 Brad Beckmannmerged with ISA event manager fix
2009-10-17 Gabe BlackISA: Fix compilation.
2009-10-15 Brad Beckmannfixed MC146818 checkpointing bug and added isa serializ...
2009-10-01 Korey Sewellinorder-debug: print out workload
2009-09-29 Lisa Hsucommit Soumyaroop's bug catch about max_insts_all_threads
2009-09-26 Steve ReinhardtO3: Add flag to control whether faulting instructions...
2009-09-26 Steve ReinhardtO3: Mark fetch stage as active if it faults.
2009-09-25 Korey Sewellinorder-debug: fix cpu tick debug message
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-09-22 Nathan Binkertpython: Move more code into m5.util allow SCons to...
2009-09-17 Korey Sewellinorder-mdu: multiplier latency fix
2009-09-16 Soumyaroop Royinorder-smt: remove hardcoded values
2009-09-15 Korey Sewellinorder-alpha-fs: edit inorder model to compile FS...
2009-09-11 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-09-01 Polina DudnikSCons fix to always make MemTest object
2009-08-25 Derek Howermerge
2009-08-25 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-23 Gabe BlackMerge with head.
2009-08-23 Gabe BlackAtomic CPU: Respect the NO_ACCESS request flag.
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtFix setting of INST_FETCH flag for O3 CPU.
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