SLICC: Remove WakeUp* import calls from ast/__init__.py
[gem5.git] / src / cpu /
2011-03-19 Nilay VaishRuby: Convert AccessModeType to RubyAccessMode
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiARM: Fix subtle bug in LDM.
2011-03-18 Ali SaidiARM: Detect and skip udelay() functions in linux kernel.
2011-03-18 Ali SaidiO3: Send instruction back to fetch on squash to seed...
2011-03-18 Ali SaidiO3: Cleanup the commitInfo comm struct.
2011-03-18 Ali SaidiMem: Fix issue with dirty block being lost when entire...
2011-03-18 Ali SaidiO3: Fix unaligned stores when cache blocked
2011-03-02 Gabe BlackSpelling: Fix the a spelling error by changing mmaped...
2011-02-25 Nilay VaishRuby: Make DataBlock.hh independent of RubySystem
2011-02-25 Timothy M. JonesO3CPU: Fix iqCount and lsqCount SMT fetch policies.
2011-02-23 Korey Sewellinorder: InstSeqNum bug
2011-02-23 Korey Sewellinorder: dyn inst initialization
2011-02-23 Korey Sewellinorder: cache packet handling
2011-02-23 Ali SaidiO3: When a prefetch causes a fault, don't record it...
2011-02-23 Ali SaidiO3: If there is an outstanding table walk don't let...
2011-02-23 Ali SaidiARM: Do something for ISB, DSB, DMB
2011-02-23 Ali SaidiARM: Fix bug that let two table walks occur in parallel.
2011-02-23 Ali SaidiO3: Fix bug when a squash occurs right before TLB miss...
2011-02-22 Brad Beckmannm5: merged in hammer fix
2011-02-18 Korey Sewellm5: merge inorder/release-notes/make_release changes
2011-02-18 Korey Sewellinorder: add names and slot #s to res. dprints
2011-02-18 Korey Sewellinorder: ignore nops in execution unit
2011-02-18 Korey Sewellinorder: update graduation unit
2011-02-18 Korey Sewellinorder: recognize isSerializeAfter flag
2011-02-18 Korey Sewellinorder: update default thread size(=1)
2011-02-18 Korey Sewellinorder: don't overuse getLatency()
2011-02-18 Korey Sewellinorder: update max. resource bandwidths
2011-02-18 Korey Sewellinorder: cleanup in destructors
2011-02-18 Korey Sewellinorder: fix cache/fetch unit memory leaks
2011-02-18 Korey Sewellinorder: remove events for zero-cycle resources
2011-02-18 Korey Sewellinorder: update pipeline interface for handling finishe...
2011-02-18 Korey Sewellinorder: remove request map, use request vector
2011-02-18 Korey Sewellinorder: add valid bit for resource requests
2011-02-18 Korey Sewellinorder: remove reqRemoveList
2011-02-18 Korey Sewellinorder: initialize res. req. vectors based on resource...
2011-02-16 Nathan Binkertmerge alpha system files into tree
2011-02-14 Gabe BlackO3: Fetch from the microcode ROM when needed.
2011-02-13 Ali SaidiO3: Fix GCC 4.2.4 complaint
2011-02-12 Korey Sewellinorder: clean up the old way of inst. scheduling
2011-02-12 Korey Sewellinorder: utilize cached skeds in pipeline
2011-02-12 Korey Sewellinorder: define iterator for resource schedules
2011-02-12 Korey Sewellinorder: stage scheduler for front/back end schedule...
2011-02-12 Korey Sewellinorder: cache instruction schedules
2011-02-12 Korey Sewellinorder: comments for resource sked class
2011-02-12 Korey Sewellinorder: remove unused file
2011-02-12 Giacomo GabrielliO3: Fix pipeline restart when a table walk completes...
2011-02-12 Ali SaidiSimpleCPU: Fix a case where a DTLB fault redirects...
2011-02-12 Giacomo GabrielliO3: Enhance data address translation by supporting...
2011-02-07 Brad Beckmannm5: added work completed monitoring support
2011-02-07 Joel HestnessTimingSimpleCPU: split data sender state fix
2011-02-07 Joel Hestnessmcpat: Adds McPAT performance counters
2011-02-04 Korey Sewellinorder: fault handling
2011-02-04 Korey Sewellinorder: pcstate and delay slots bug
2011-02-04 Korey Sewellinorder: add a fetch buffer to fetch unit
2011-02-04 Korey Sewellinorder: overload find-req fn
2011-02-04 Korey Sewellinorder: implement separate fetch unit
2011-02-04 Korey Sewellinorder: cache port blocking
2011-02-04 Korey Sewellinorder: stage width as a python parameter
2011-02-04 Korey Sewellinorder: multi-issue branch resolution
2011-02-04 Korey Sewellinorder: pipe. stage inst. buffering
2011-02-04 Korey Sewellinorder: change skidBuffer to list instead of queue
2011-02-04 Korey Sewellinorder: activity tracking bug
2011-02-04 Gabe BlackFault: Rename sim/fault.hh to fault_fwd.hh to distingui...
2011-02-04 Gabe BlackConfig: Keep track of uncached and cached ports separately.
2011-02-03 Gabe BlackO3: Fix a style bug in O3.
2011-02-02 Gabe BlackX86: Add L1 caches for the TLB walkers.
2011-01-18 Matt HorsnellO3: Fix some variable length instruction issues with...
2011-01-18 Matt HorsnellO3: Don't test misprediction on load instructions until...
2011-01-18 Ali SaidiO3: Keep around the last committed instruction and...
2011-01-18 Ali SaidiO3: Don't try to scoreboard misc registers.
2011-01-18 Matt HorsnellO3: Fix corner cases where multiple squashes/fetch...
2011-01-18 Matt HorsnellO3: Fix mispredicts from non control instructions.
2011-01-18 Matt HorsnellO3: Fixes the way prefetches are handled inside the...
2011-01-18 Ali SaidiO3: Support timing translations for O3 CPU fetch.
2011-01-18 Ali SaidiARM: Add support for moving predicated false dest opera...
2011-01-18 Min Kyu JeongO3: Fixes fetch deadlock when the interrupt clears...
2011-01-12 Korey Sewellinorder: fix RUBY_FS build
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2011-01-08 Steve Reinhardtinorder: replace schedEvent() code with reschedule().
2011-01-08 Steve Reinhardtinorder: get rid of references to mainEventQueue.
2011-01-03 Steve ReinhardtMove sched_list.hh and timebuf.hh from src/base to...
2011-01-03 Steve ReinhardtMake commenting on close namespace brackets consistent.
2010-12-23 Nilay VaishThis patch removes the WARN_* and ERROR_* from src...
2010-12-22 Steve Reinhardtmemtest: delete some crufty dead code
2010-12-20 Gabe BlackStyle: Replace some tabs with spaces.
2010-12-08 Ali SaidiO3: Allow a store entry to store up to 16 bytes (instea...
2010-12-08 Ali SaidiO3: Support squashing all state after special instruction
2010-12-08 Giacomo GabrielliO3: Make all instructions that write a misc. register...
2010-12-08 Min Kyu JeongO3: Support SWAP and predicated loads/store in ARM.
2010-12-08 Ali SaidiARM: Support switchover with hardware table walkers
2010-12-01 Nilay Vaishruby: Converted old ruby debug calls to M5 debug calls
2010-11-23 Gabe BlackX86: Loosen an assert for x86 and connect the APIC...
2010-11-20 Ali SaidiSCons: Support building without an ISA
2010-11-18 Gabe BlackO3: Fix fp destination register flattening, and index...
2010-11-16 Gabe BlackO3: Make O3 support variably lengthed instructions.
2010-11-15 Ali SaidiO3: reset architetural state by calling clear()
2010-11-15 Giacomo GabrielliCPU/ARM: Add SIMD op classes to CPU models and ARM...
2010-11-15 Min Kyu JeongO3: prevent a squash when completeAcc() modifies misc...
2010-11-15 Ali SaidiSCons: Cleanup SCons output during compile
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