mem: Use shared_ptr for Ruby Message classes
[gem5.git] / src / cpu /
2014-10-16 Andreas Sandbergcpu: Probe points for basic PMU stats
2014-10-16 Andreas Sandbergcpu: Add branch predictor PMU probe points
2014-10-11 Andrew Lukefahrcpu: Fix o3 SMT IQCount bug
2014-10-09 Mitch Hayengacpu: Remove Ozone CPU from the source tree
2014-09-27 Andreas Hanssonarch: Use const StaticInstPtr references where possible
2014-09-27 Andreas Hanssonscons: Address issues related to gcc 4.9.1
2014-09-27 Andreas Hanssonmisc: Fix a bunch of minor issues identified by static...
2014-09-20 Mitch Hayengacpu: Remove unused deallocateContext calls
2014-09-20 Mitch Hayengaalpha,arm,mips,power,x86,cpu,sim: Cleanup activate...
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 Wendy Elsassercpu: Update DRAM traffic gen
2014-09-20 Andreas Hanssonbase: Clean up redundant string functions and use C++11
2014-09-20 Mitch Hayengacpu: Add ExecFlags debug flag
2014-09-20 Dam Sunwoocpu: use probes infrastructure to do simpoint profiling
2014-09-19 Andreas Hanssonarch: Pass faults by const reference where possible
2014-09-19 Andreas Hanssoncpu: Use a deque in o3 rename instruction queue
2014-09-19 Andreas Hanssonmisc: Use safe_cast when assumptions are made about...
2014-09-12 Andrew Bardsleycpu: Fix memory access in Minor not setting parent...
2014-09-12 Andrew Bardsleystyle: Fix line continuation, especially in debug messages
2014-09-12 Andreas Hanssonminor: Fix typo in DPRINTF for Minor branch prediction
2014-09-09 Mitch Hayengacpu: Only iterate over possible threads on the o3 cpu
2014-09-09 Andreas Hanssonmisc: Fix a number of unitialised variables and members
2014-09-03 Andreas Hanssonbase: Use the global Mersenne twister throughout
2014-05-13 Curtis Dunhammem: Refactor assignment of Packet types
2014-09-03 Mitch Hayengacpu: Fix o3 drain bug
2014-04-29 Curtis Dunhamarm: use condition code registers for ARM ISA
2014-09-03 Dam Sunwoocpu: fix bimodal predictor to use correct global histor...
2014-09-03 Mitch Hayengacpu: Fix cache blocked load behavior in o3 cpu
2014-09-03 Mitch Hayengacpu: Fix o3 quiesce fetch bug
2014-09-03 Mitch Hayengacpu: Fix SMT scheduling issue with the O3 cpu
2014-09-03 Mitch Hayengacpu: Fix incorrect speculative branch predictor behavior
2014-09-03 Mitch Hayengacpu: Add a fetch queue to the o3 cpu
2014-09-03 Mitch Hayengacpu: Fix o3 front-end pipeline interlock behavior
2014-09-03 Mitch Hayengacpu: Change writeback modeling for outstanding instructions
2014-09-03 Andreas Sandbergarch, cpu: Factor out the ExecContext into a proper...
2014-09-01 Nilay Vaishmem: change the namespace Message to ProtoMessage
2014-09-01 Nilay Vaishruby: eliminate type Time
2014-08-13 Andreas Sandbergscons: Build the branch predictor for all CPUs
2014-08-13 Andreas Sandbergcpu: Don't forward declare RefCountingPtr
2014-08-13 Andreas Hanssoncpu: Modernise the branch predictor (STL and C++11)
2014-08-10 Andreas Hanssoncpu: Ensure the traffic generator suppresses non-memory...
2014-07-23 Andrew Bardsleycpu: `Minor' in-order CPU model
2014-06-30 Anthony Gutierrezcpu: implement a bi-mode branch predictor
2014-06-21 Binh Phamo3: make dispatch LSQ full check more selective
2014-06-21 Binh Phamo3: split load & store queue full cases in rename
2014-06-01 Steve Reinhardtstyle: eliminate equality tests with true and false stable_2014_08_26
2014-05-23 Nilay Vaishcpu: o3: remove stat totalCommittedInsts
2014-05-09 Andrew Bardsleycpu: Useful getters for ActivityRecorder
2014-05-09 Andrew Bardsleycpu: Add flag name printing to StaticInst
2014-05-09 Andrew Bardsleycpu: Timebuf const accessors
2014-05-09 Geoffrey Blakearch, arm: Preserve TLB bootUncacheability when switchi...
2014-05-09 Curtis Dunhamcpu: add more instruction mix statistics
2014-05-09 Akash Bagdiacpu, arm: Allow the specification of a socket field
2014-04-23 Mitchell Hayengacpu: Fix setTranslateLatency() bug for squashed instruc...
2014-04-01 Mitch Hayengacpu: Fix case where o3 lsq could print out uninitialize...
2014-04-23 Dam Sunwoocpu: Add O3 CPU width checks
2014-04-19 Faissal Sleimano3: Fix occupancy checks for SMT
2014-04-09 Andreas Sandbergkvm, x86: Add initial support for multicore simulation
2014-03-25 Marco Elvercpu: o3: lsq: Fix TSO implementation
2014-03-23 Neha Agarwalcpu: DRAM Traffic Generator
2014-03-23 Stan Czerniawskicpu: Add basic check to TrafficGen initial state
2014-03-16 Andreas Sandbergkvm: Clean up signal handling
2014-03-16 Andreas Sandbergkvm: x86: Adjust PC to remove the CS segment base address
2014-03-16 Andreas Sandbergkvm: x86: Add support for x86 INIT and STARTUP handling
2014-03-12 Paul Rosenfeldalpha: Small removal of dead comments/code from alpha ISA
2014-03-07 Andreas Hanssoncpu: Make CPU and ThreadContext getters const
2014-03-07 Mitch Hayengascons: Fixes uninitialized warnings issued by clang
2014-03-03 Andreas Sandbergkvm: x86: Always assume segments to be usable
2014-03-03 Andreas Sandbergkvm: Initialize signal handlers from startupThread()
2014-03-02 Christopher Torngcpu: Enable fast-forwarding for MIPS InOrderCPU and...
2014-02-20 Andreas Sandbergkvm: Add support for multi-system simulation
2014-02-09 Andreas Sandbergcpu: simple: Add support for using branch predictors
2014-01-30 Xiangyu Dongcpu: fix bug when TrafficGen deschedules event
2014-01-24 ARM gem5 Developersarm: Add support for ARMv8 (AArch64 & AArch32)
2014-01-24 Geoffrey Blakechecker: CheckerCPU handling of MiscRegs was incorrect
2014-01-24 Ali Saidiarch, cpu: Add support for flattening misc register...
2014-01-24 Giacomo Gabriellicpu: Add support for Memory+Barrier instruction types...
2014-01-24 Ali Saidicpu: Add support for instructions that zero cache lines.
2014-01-24 Ali Saidicpu: Add CPU support for generatig wake up events when...
2014-01-24 Dam Sunwoomem: per-thread cache occupancy and per-block ages
2014-01-24 Matt Horsnellbase: add support for probe points and common probes
2014-01-24 Matt Horsnellmem: track per-request latencies and access depths...
2014-01-24 Andreas Hanssoncpu: Relax check on squashed non-speculative instructions
2014-01-24 Dam Sunwoocpu: remove faulty simpoint basic block inst count...
2013-12-03 Nilay Vaishcpu: call BaseCPU startup() function in o3 cpu
2013-10-15 Andreas Sandbergkvm: Set the perf exclude_host attribute if available
2013-11-26 Andreas Sandbergkvm: Remove the unused hostFreq member from BaseKvmCPU
2013-11-25 Steve Reinhardt... sim: simulate with multiple threads and event queues
2013-11-15 Anthony Gutierrezcpu: allow the fetch buffer to be smaller than a cache...
2013-11-15 Andreas Hanssoncpu: Fix Checker register index use
2013-10-31 Faissal Sleimancpu: Construct ROB with cpu params struct instead of...
2013-10-31 Ali Saidicpu: Fix O3 issuse with load+barrier instructions.
2013-10-17 Matt Horsnellcpu: add consistent guarding to *_impl.hh files.
2013-10-17 Faissal Sleimancpu: Removing an unused variable in rename
2013-10-17 Faissal Sleimancpu: Change IEW DPRINTF to use IEW debug flag
2013-10-17 Faissal Sleimancpu: Put in assertions to check for maximum supported...
2013-10-17 Ali Saidicpu: Fix O3 uncacheable load that is replayed but misse...
2013-10-16 Andreas Sandbergkvm: Fix latency calculation of IPR accesses
2013-10-15 Yasuko Eckertarch/x86: add support for explicit CC register file
2013-10-15 Yasuko Eckertcpu: add a condition-code register class
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