o3 cpu: remove some unused buggy functions in the lsq
[gem5.git] / src / cpu /
2012-12-06 Nathanael Premillieuo3 cpu: remove some unused buggy functions in the lsq
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-11-02 Andreas Sandbergcpu: O3 add a header declaring the DerivO3CPU
2012-11-02 Andreas Sandbergcpu: Add header files for checker CPUs
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces
2012-11-02 Dam SunwooARM: dump stats and process info on context switches
2012-11-02 Mrinmoy Ghosho3: Fix a couple of issues with the local predictor.
2012-10-15 Nilay Vaishmemtest: move check on outstanding requests
2012-10-15 Andreas HanssonPort: Add protocol-agnostic ports in the port hierarchy
2012-10-15 Andreas HanssonFix: Address a few minor issues identified by cppcheck
2012-10-15 Andreas HanssonRegression: Use CPU clock and 32-byte width for L1...
2012-09-25 Ali SaidiO3: Pack the comm structures a bit better to reduce...
2012-09-25 Ali SaidiARM: Squash outstanding walks when instructions are...
2012-09-25 Andreas Sandbergsim: Move CPU-specific methods from SimObject to the...
2012-09-25 Djordje KovacevicCPU: Add abandoned instructions to O3 Pipe Viewer
2012-09-21 Andreas HanssonTrafficGen: Add a basic traffic generator
2012-09-19 Andreas HanssonAddrRange: Transition from Range<T> to AddrRange
2012-09-13 Joel HestnessBase CPU: Initialize profileEvent to NULL
2012-09-12 Anthony Gutierrezstats: remove duplicate instruction stats from the...
2012-09-11 Nilay VaishRuby: Use uint8_t instead of uint8 everywhere
2012-09-07 Ali SaidiO3: Get rid of incorrect assert in RAS.
2012-09-07 Andreas HanssonParam: Transition to Cycles for relevant parameters
2012-08-28 Andreas HanssonClock: Add a Cycles wrapper class and use where applicable
2012-08-28 Andreas HanssonClock: Rework clocks to avoid tick-to-cycle transformations
2012-08-28 Andreas HanssonPort: Stricter port bind/unbind semantics
2012-08-28 Andreas HanssonChecker: Fix checker CPU ports
2012-08-27 Nilay VaishRuby: Remove RubyEventQueue
2012-08-22 Andreas HanssonPacket: Remove NACKs from packet and its use in endpoints
2012-08-21 Andreas HanssonCPU: Remove overloaded function_trace_start parameter
2012-08-21 Andreas HanssonClock: Make Tick unsigned and remove UTick
2012-08-21 Andreas HanssonClock: Move the clock and related functions to ClockedO...
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-08-06 Steve Reinhardtprocess: add progName() virtual function
2012-07-27 Anthony Gutierrezchecker: make checker cpu id match its host's cpu id
2012-07-11 Brad Beckmannruby: remove the cpu assumptions for the random tester
2012-07-11 Brad Beckmanncpu: added assertions to ensure the correct proxies...
2012-07-09 Andreas HanssonPort: Align port names in C++ and Python
2012-07-09 Andreas HanssonPort: Move retry from port base class to Master/SlavePort
2012-07-09 Andreas HanssonFix: Address a few benign memory leaks
2012-06-29 Nathanael PremillieuO3: Track if the RAS has been pushed or not to pop...
2012-06-08 Andreas HanssonTiming CPU: Remove a redundant port pointer
2012-06-05 Anthony Gutierrezcpu: Don't init simple and inorder CPUs if they are...
2012-06-05 Ali SaidiISA: Back-out NoopMachInst as a StaticInstPtr change.
2012-06-05 Ali SaidiO3: Clean up the O3 structures and try to pack them...
2012-06-05 Ali Saidisim: Remove FastAlloc
2012-06-04 Gabe BlackISA: Turn the ExtMachInst NoopMachinst into the StaticI...
2012-05-31 Andreas HanssonBus: Split the bus into a non-coherent and coherent bus
2012-05-30 Andreas HanssonPacket: Unify the use of PortID in packet and port
2012-05-26 Gabe BlackISA,CPU: Generalize and split out the components of...
2012-05-26 Gabe BlackCPU: Merge the predecoder and decoder.
2012-05-25 Gabe BlackISA: Make the decode function part of the ISA's decoder.
2012-05-25 Gabe BlackCPU: Simplify the implementation of the decode cache.
2012-05-25 Gabe BlackDecode: Make the Decoder class defined per ISA.
2012-05-10 Ali Saidigem5: fix some iterator use and erase bugs
2012-05-10 Ali Saidigem5: fix a number of use after free issues
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-25 Andreas HanssonMEM: Add the PortId type and a corresponding id field...
2012-04-15 Gabe BlackCPU: Tidy up some formatting and a DPRINTF in the simpl...
2012-04-14 Andreas HanssonRuby: Use MasterPort base-class pointers where possible
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-04-14 Andreas Hanssonclang/gcc: Fix compilation issues with clang 3.0 and...
2012-04-07 Brad Beckmannrubytest: remove spurious printf
2012-04-06 Brad Beckmannrubytest: seperated read and write ports.
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-04-05 Tushar KrishnaNetworkTest: remove unnecessary memory allocation
2012-04-03 Andreas HanssonAtomic: Remove the physmem_port and access memory directly
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-30 Andreas HanssonCPU: Unify initMemProxies across CPUs and simulation...
2012-03-22 Andreas HanssonScons: Remove Werror=False in SConscript files
2012-03-21 Andrew LukefahrO3: Fix sizing of decode to rename skid buffer.
2012-03-21 Brian GraysonO3: Fix size of skid buffer between fetch and decode...
2012-03-19 Andreas Hanssongcc: Clean-up of non-C++0x compliant code, first steps
2012-03-19 Andreas Hanssonclang: Fix recently introduced clang compilation errors
2012-03-11 Brian GraysonO3: Add fatal when fetchWidth > Impl::MaxWidth.
2012-03-09 Geoffrey BlakeO3/Ozone: Eliminate dead code counting software prefetc...
2012-03-09 Geoffrey BlakeCheckerCPU: Add function stubs to non-ARM ISA source...
2012-03-09 Geoffrey BlakeCheckerCPU: Make CheckerCPU runtime selectable instead...
2012-03-02 Steve ReinhardtDynInst: get rid of dead MyHash code.
2012-03-02 Andreas HanssonCPU: Check that the interrupt controller is created...
2012-03-01 Nilay Vaishx86: Fix switching of CPUs
2012-02-24 Andreas HanssonRuby: Simplify tester ports by not using SimpleTimingPort
2012-02-24 Andreas HanssonMEM: Move all read/write blob functions from Port to...
2012-02-24 Andreas HanssonMEM: Make port proxies use references rather than pointers
2012-02-24 Andreas HanssonMEM: Move port creation to the memory object(s) constru...
2012-02-24 Andreas HanssonCPU: Round-two unifying instr/data CPU ports across...
2012-02-13 Mrinmoy GhoshBPred: Fix RAS to handle predicated call/return instruc...
2012-02-13 Mrinmoy GhoshBP: Fix several Branch Predictor issues.
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-12 Anthony Gutierrezcpu: add separate stats for insts/ops both globally...
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-10 Nilay VaishO3 CPU: Improve handling of delayed commit flag
2012-02-10 Nilay VaishO3 CPU: Strengthen condition for handling interrupts
2012-02-10 Nilay VaishO3 CPU: Provide the squashing instruction
2012-02-10 Nilay VaishO3 Fetch: Check if PC is pointing to Microcode ROM
2012-02-10 Gabe BlackSE/FS: Record the system pointer all the time for the...
2012-02-07 Gabe BlackChecker: Access workload element 0 only if there is...
2012-02-07 Gabe BlackFaults: Turn off arch/faults.hh
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
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