X86: Implement the sysret instruction in long mode.
[gem5.git] / src / cpu /
2009-02-25 Gabe BlackCPU: Implement translateTiming which defers to translat...
2009-02-25 Gabe BlackISA: Replace the translate functions in the TLBs with...
2009-02-25 Gabe BlackCPU: Get rid of translate... functions from various...
2009-02-23 Nathan Binkertdebug: Move debug_break into src/base
2009-02-20 Korey SewellRemove unnecessary building of FreeList/RenameMap in...
2009-02-16 Steve ReinhardtFixes to get prefetching working again.
2009-02-11 Nathan Binkertstyle
2009-02-10 Korey SewellConfigs: Add support for the InOrder CPU model
2009-02-10 Korey SewellInOrder: Import new inorder CPU model from MIPS.
2009-02-10 Korey SewellExeTrace: Allow subclasses of the tracer to define...
2009-02-10 Korey SewellCPU: Prepare CPU models for the new in-order CPU model.
2009-02-01 Gabe BlackCPU: Don't always reset the micro pc on faults. Let...
2009-02-01 Gabe BlackX86: Make sure the predecoder is cleared out for interr...
2009-01-31 Ali SaidiConfig: Cause a fatal() when a parameter without a...
2009-01-26 Gabe BlackCPU: Add a setCPU function to the interrupt objects.
2009-01-24 Nathan Binkertcpu: provide a wakeup mechanism that can be used to...
2009-01-21 Nathan Binkerto3cpu: give a name to the activity recorder for better...
2009-01-20 Nathan Binkertthread_context: move getSystemPtr so SE mode can get...
2009-01-13 Nathan BinkertSCons: centralize the Dir() workaround for newer versio...
2009-01-12 Richard StrongThis fix addresses an ill formed if statement that...
2009-01-07 Gabe BlackTracing: Make tracing aware of macro and micro ops.
2008-12-17 Steve ReinhardtMake Alpha pseudo-insts available from SE mode.
2008-12-17 Gabe BlackSPARC: Truncate syscall args and return values appropri...
2008-12-06 Nathan Binkerteventq: use the flags data structure
2008-11-14 Gabe BlackCPU: Refactor read/write in the simple timing CPU.
2008-11-10 Clint SmullenO3CPU: Make the instcount debugging stuff per-cpu.
2008-11-10 Nathan Binkertmem: update stuff for changes to Packet and Request
2008-11-10 Gabe BlackCPU: Make unaligned accesses work in the timing simple...
2008-11-10 Gabe BlackX86: Make the timing simple CPU handle variable length...
2008-11-05 Lisa HsuRight now a single thread cpu 1 could get assigned...
2008-11-04 Lisa Hsuget rid of all instances of readTid() and getThreadNum...
2008-11-03 Lisa HsuAdd in Context IDs to the simulator. From now on,...
2008-11-03 Lisa HsuMake it so that all thread contexts are registered...
2008-11-03 Lisa Hsumake BaseCPU the provider of _cpuId, and cpuId() instea...
2008-10-27 Clint SmullenCPU: The API change to EventWrapper did not get propag...
2008-10-23 Lisa Hsus/cpu_id/cpuId in o3 (to be consistent and match style...
2008-10-21 Nathan Binkertstyle: Use the correct m5 style for things relating...
2008-10-20 Ali SaidiO3CPU: Undo Gabe's changes to remove hwrei and simpalch...
2008-10-13 Gabe BlackCPU: Explain why some code is commented out.
2008-10-13 Gabe BlackX86: Make the MicroPC type 16 bit.
2008-10-13 Gabe BlackX86: Don't fetch in the simple CPU if you're in the...
2008-10-13 Gabe BlackGet rid of old RegContext code.
2008-10-12 Gabe BlackCPU: Make the highest order bit in the micro pc determi...
2008-10-12 Gabe BlackCPU: Create a microcode ROM object in the CPU which...
2008-10-12 Gabe BlackX86: Fix the ordering of special physical address ranges.
2008-10-12 Gabe BlackX86: Make APICs communicate through the memory system.
2008-10-12 Gabe BlackX86: Make the local APIC accessible through the memory...
2008-10-12 Gabe BlackTurn Interrupts objects into SimObjects. Also, move...
2008-10-12 Gabe BlackCPU: Eliminate the get_vec function.
2008-10-11 Gabe BlackCPU: Add a getInterruptController function
2008-10-11 Gabe BlackCPU: Eliminate the simPalCheck funciton.
2008-10-11 Gabe BlackCPU: Eliminate the hwrei function.
2008-10-10 Nathan BinkertSimObjects: Clean up handling of C++ namespaces.
2008-10-09 Nathan Binkerteventq: convert all usage of events to use the new...
2008-10-09 Gabe BlackO3: Generaize the O3 IMPL class so it isn't split out...
2008-10-09 Gabe BlackO3: Generaize the O3 dynamic instruction class so it...
2008-10-09 Gabe BlackO3: Generalize the O3 CPU object so it isn't split...
2008-10-09 Gabe BlackCPU: Fix where setMicroPC was being called instead...
2008-09-28 Nathan Binkertgcc: Add extra parens to quell warnings.
2008-09-26 Kevin LimO3CPU: Fix thread writeback logic.
2008-09-26 Kevin LimO3CPU: Add a hack to ensure that nextPC is set correctl...
2008-09-22 Nathan Binkertgcc: Version 4.3 is pretty anal about shadowing types...
2008-09-10 Ali Saidistyle: Remove non-leading tabs everywhere they shouldn...
2008-08-20 Gabe BlackCPU: Get rid of two more duplicated CPU params.
2008-08-18 Richard StrongChanged BaseCPU::ProfileEvent's interval member to...
2008-08-11 Nathan Binkertparams: Convert the CPU objects to use the auto generat...
2008-08-04 Nathan Binkertsockets: Add a function to disable all listening sockets.
2008-07-15 Steve ReinhardtUse ReadResp instead of LoadLockedResp for LoadLockedRe...
2008-07-01 Ali SaidiRemove delVirtPort() and make getVirtPort() only return...
2008-07-01 Ali SaidiMake the cached virtPort have a thread context so it...
2008-07-01 Ali SaidiAfter a checkpoint (and thus a stats reset), the not_id...
2008-06-28 Steve ReinhardtAutomated merge after backout.
2008-06-28 Steve ReinhardtBacked out changeset 94a7bb476fca: caused memory leak.
2008-06-24 Ali SaidiAutomated merge with repo.m5sim.org/m5-stable
2008-06-21 Steve ReinhardtGenerate more useful error messages for unconnected...
2008-06-18 Nathan BinkertAtomicSimpleCPU: Separate data stalls from instruction...
2008-06-18 Nathan BinkertThreadState: Ensure that kernelStats is properly initia...
2008-06-16 Nathan Binkertport: Clean up default port setup and port switchover...
2008-06-12 Gabe BlackCPU: Make the simple cpu trace data for loads/stores.
2008-04-10 Ali SaidiSCons: add comments to SConscript documenting bug worka...
2008-04-08 Ali SaidiSCons: Manually specifying header only directories...
2008-03-24 Steve ReinhardtDon't FastAlloc MSHRs since we don't allocate them...
2008-03-07 Gabe BlackMerge
2008-03-06 Vilas SridharanO3CPU: Don't call dumpInsts if DEBUG is not defined
2008-02-27 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-02-27 Korey SewellAdd comments in code to describe bug conditions.
2008-02-27 Korey SewellFix Load/Store Queue squashing after a SMT thread is...
2008-02-27 Korey SewellFix offset in removeThread() function so that float...
2008-02-27 Gabe BlackTLB: Make a TLB base class and put a virtual demapPage...
2008-02-14 Ali SaidiCPU: move the PC Events code to a place where the code...
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-10 Steve ReinhardtFix #include lines for renamed cache files.
2008-02-06 Stephen HinesMake the Event::description() a const function
2008-02-06 Stephen HinesAdd base ARM code to M5
2008-01-14 Ke MengThe reason is that the event is supposed to put the...
2008-01-02 Steve ReinhardtAdd ReadRespWithInvalidate to handle multi-level cohere...
2008-01-02 Steve ReinhardtAdditional comments and helper functions for PrintReq.
2008-01-02 Steve ReinhardtAdd functional PrintReq command for memory-system debug...
2007-12-18 Ali SaidiCheckpointing: Fix a bug in the simulation script when...
2007-12-16 Ali SaidiCPU: Update where the simple cpus read their cpu id...
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