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up arty a7 frequency to 40 mhz
[ls2.git]
/
src
/
crg.py
2022-03-25
Luke Kenneth Casso...
increase time for power-on-delay to 2^25 in ECP5
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2022-03-24
Luke Kenneth Casso...
increase delay on ECP5 ulx3s
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2022-03-24
Luke Kenneth Casso...
check ulx3s, add CRG support for ulx3s
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2022-02-23
Luke Kenneth Casso...
invert CRG reset on PLL see if it makes any difference
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2022-02-23
Luke Kenneth Casso...
add comments about DRAM sync clock being identical...
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2022-02-16
Luke Kenneth Casso...
wildcards never ok. update comments
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2022-02-16
Luke Kenneth Casso...
add copyright notices
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2022-02-16
Luke Kenneth Casso...
update ECP5 PLL to accept parameters for setting arbitr...
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2022-02-13
Luke Kenneth Casso...
rename examples to src
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