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radeon: enable Hyper-Z on r600g and radeonsi by default
[mesa.git]
/
src
/
gallium
/
drivers
/
nouveau
/
codegen
/
nv50_ir_emit_nvc0.cpp
2014-07-10
Ilia Mirkin
nvc0/ir: fix encoding of offset register into interpola...
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2014-07-01
Ilia Mirkin
nvc0/ir: fix emitting vertex stream
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2014-05-28
Alexandre Courbot
nvc0/ir: use SM35 ISA with GK20A
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2014-04-28
Ilia Mirkin
nv50/ir: change texture offsets to ValueRefs, allow...
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2014-04-28
Ilia Mirkin
nvc0/ir: add support for new bitfield manipulation...
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2014-04-26
Ilia Mirkin
nvc0: add support for PIPE_CAP_SAMPLE_SHADING
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2014-04-07
Ilia Mirkin
nvc0: add support for texture gather
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2014-04-07
Ilia Mirkin
nvc0: enable texture query lod
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2014-02-07
Christoph Bumiller
nvc0/ir/emit: hardcode vertex output stream to 0 for now
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2014-01-27
Ilia Mirkin
nouveau/codegen: set dType to S32 for OP_NEG U32
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2013-09-11
Johannes Obermayr
Move nv30, nv50 and nvc0 to nouveau.
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