radeonsi: Fix sampler views for depth textures.
[mesa.git] / src / gallium / drivers / radeon / SIInstructions.td
2012-10-26 Michel Dänzerradeon/llvm: Add intrinsic for reading SI FRONT_FACE...
2012-10-10 Vincent Lejeuneradeon/llvm: use floor intrinsic instead of llvm.AMDIL...
2012-09-17 Michel Dänzerradeon/llvm: Match integer add/sub for SI.
2012-09-17 Michel Dänzerradeon/llvm: Complete integer comparison patterns for SI.
2012-09-17 Michel Dänzerradeon/llvm: Match AMDGPUfract on SI.
2012-09-17 Michel Dänzerradeon/llvm: Match int_AMDGPU_floor for SI.
2012-09-17 Michel Dänzerradeon/llvm: Match vector logical operations on SI.
2012-09-14 Christian Königradeon/llvm: Support frint on SI
2012-09-13 Tom Stellardradeon/llvm: Fix lowering of vbuild
2012-09-13 Tom Stellardradeon/llvm: Support fmul on SI
2012-09-11 Tom Stellardradeonsi: Handle position input parameter for pixel...
2012-09-07 Michel Dänzerradeon/llvm: Match fexp2 for SI.
2012-09-06 Michel Dänzerradeon/llvm: Add intrinsic for enabling whole quad...
2012-09-05 Tom Stellardradeon/llvm: Fix operand ordering for V_CNDMASK_B32
2012-09-05 Tom Stellardradeon/llvm: Use correct float->int conversion opcode...
2012-09-04 Tom Stellardradeon/llvm: Fix encoding of V_CNDMASK_B32
2012-08-31 Tom Stellardradeon/llvm: Rework how immediate operands are handled...
2012-08-31 Tom Stellardradeon/llvm: Add support for RCP instruction on SI
2012-08-31 Tom Stellardradeon/llvm: Support AMDGPUfmin DAG node on SI
2012-08-29 Tom Stellardradeon/llvm: Create a register class for the M0 register
2012-08-29 Tom Stellardradeon/llvm: Set the neverHasSideEffects bit on more...
2012-08-28 Michel Dänzerradeon/llvm: Handle TGSI KIL opcode for SI.
2012-08-28 Michel Dänzerradeon/llvm: Basic support for SI EXEC register.
2012-08-27 Michel Dänzerradeonsi: Use FP16 shader export format when necessary...
2012-08-23 Tom Stellardradeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SI
2012-08-15 Tom Stellardradeon/llvm: Lower loads from USE_SGPR adddress space...
2012-08-15 Tom Stellardradeon/llvm: Add live-in registers during DAG lowering
2012-08-02 Tom Stellardradeon/llvm: Add support for more f32 CMP instructions...
2012-08-02 Tom Stellardradeon/llvm: Add support for fneg on SI
2012-08-02 Tom Stellardradeon/llvm: Add support for fp_to_sint on SI
2012-08-02 Michel Dänzerradeonsi: Handle TGSI DIV opcode.
2012-07-31 Tom Stellardradeon/llvm: Add pseudo-support for 64-bit immediate...
2012-07-30 Tom Stellardradeon/llvm: Rename all AMDIL* classes to AMDGPU*
2012-07-27 Tom Stellardradeon/llvm: Add instruction defs for branches on SI
2012-07-27 Tom Stellardradeon/llvm: Fix VOPC and V_CNDMASK encoding
2012-07-27 Tom Stellardradeon/llvm: Add special nodes for SALU operations...
2012-07-27 Tom Stellardradeon/llvm: Add bitconvert patterns for SI
2012-07-11 Tom Stellardradeon/llvm: Use multiclasses for floating point loads
2012-06-12 Thomas Stellardradeonsi: Handle SUB_f32.
2012-06-06 Tom Stellardradeon/llvm: Remove AMDIL VCREATE* instructions
2012-06-06 Tom Stellardradeon/llvm: Remove AMDIL LOADCONST* instructions
2012-05-29 Tom Stellardradeonsi: Remove use.sgpr* intrinsics, use load instruc...
2012-05-29 Tom Stellardradeonsi: Handle TGSI CONST registers
2012-05-25 Tom Stellardradeon/llvm: Use a custom inserter to lower CLAMP
2012-05-25 Tom Stellardradeon/llvm: Use a custom inserter to lower FABS
2012-05-24 Tom Stellardradeon/llvm: Remove auto-generated AMDIL->ISA conversio...
2012-05-17 Tom Stellardradeon/llvm: Remove AMDIL MAD instruction defs
2012-05-17 Tom Stellardradeon/llvm: Remove AMDIL floating-point ADD instructio...
2012-05-17 Tom Stellardradeon/llvm: Add custom SDNodes for MAX
2012-05-14 Michel Dänzerradeonsi: Flesh out shader interpolation related code.
2012-05-11 Marek OlšákMerge branch 'gallium-userbuf'
2012-05-10 Tom Stellardradeon/llvm: Add some comments
2012-05-09 Tom Stellardradeon/llvm: Make sure the LOAD_CONST def uses the...
2012-05-08 Tom Stellardradeon/llvm: Remove the ReorderPreloadInstructions...
2012-04-23 Tom Stellardr600g/llvm: Let ISel handle lowering to {INSERT,EXTRACT...
2012-04-13 Tom Stellardradeonsi: initial WIP SI code