intel/eu: Plumb header present bit to codegen helpers for HDC messages.
[mesa.git] / src / intel / compiler / brw_eu_defines.h
2017-12-31 Kenneth Graunkei965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.
2017-12-06 Jose Maria Casanov... i965/fs: Add byte scattered read message and fs support
2017-12-06 Jose Maria Casanov... i965/fs: Add byte scattered write message and fs support
2017-12-06 Alejandro Piñeiroi965/fs: Add remove_extra_rounding_modes optimization
2017-12-06 Alejandro Piñeiroi965/fs: Define new shader opcode to set rounding modes
2017-10-20 Matt Turneri965: Add align1 ternary instruction disassembler support
2017-10-20 Matt Turneri965: Add align1 ternary instruction field encodings
2017-08-21 Matt Turneri965: Hide the register type hardware encodings
2017-08-21 Matt Turneri965: Use separate enums for register vs immediate...
2017-05-26 Jason Ekstrandi965: Move SF compilation to the compiler
2017-05-03 Rafael Antognollii965: Move enums to brw_compiler.h.
2017-04-14 Samuel Iglesias... i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcod...
2017-03-13 Iago Toral Quirogaintel: fix compiler build
2017-03-13 Jason Ekstrandi965: Move the back-end compiler to src/intel/compiler