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intel/eu: Plumb header present bit to codegen helpers for HDC messages.
[mesa.git]
/
src
/
intel
/
compiler
/
brw_eu_defines.h
2017-12-31
Kenneth Graunke
i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.
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2017-12-06
Jose Maria Casanov...
i965/fs: Add byte scattered read message and fs support
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2017-12-06
Jose Maria Casanov...
i965/fs: Add byte scattered write message and fs support
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2017-12-06
Alejandro Piñeiro
i965/fs: Add remove_extra_rounding_modes optimization
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2017-12-06
Alejandro Piñeiro
i965/fs: Define new shader opcode to set rounding modes
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2017-10-20
Matt Turner
i965: Add align1 ternary instruction disassembler support
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2017-10-20
Matt Turner
i965: Add align1 ternary instruction field encodings
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2017-08-21
Matt Turner
i965: Hide the register type hardware encodings
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2017-08-21
Matt Turner
i965: Use separate enums for register vs immediate...
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2017-05-26
Jason Ekstrand
i965: Move SF compilation to the compiler
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2017-05-03
Rafael Antognolli
i965: Move enums to brw_compiler.h.
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2017-04-14
Samuel Iglesias...
i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcod...
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2017-03-13
Iago Toral Quiroga
intel: fix compiler build
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2017-03-13
Jason Ekstrand
i965: Move the back-end compiler to src/intel/compiler
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