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cpu: Apply the ARM TLB rework to the O3 checker CPU.
[gem5.git] / src / mem / DRAMCtrl.py
2019-06-06 Matthew Porembamem: Option to toggle DRAM low-power states blob | commitdiff | raw
2019-02-12 Andreas Sandbergpython: Don't assume SimObjects live in the global... blob | commitdiff | raw | diff to current
2018-09-07 Matteo Andreozzimem: Make DRAMCtrl a QoS-aware Memory Controller blob | commitdiff | raw | diff to current
2018-05-18 Wendy Elsassermem: Add support for more flexible DRAM timing and... blob | commitdiff | raw | diff to current
2018-02-09 Wendy ElsasserFix DDR4_2400_8x8 DRAMCTRL configuration blob | commitdiff | raw | diff to current
2017-02-14 Wendy Elsassermem: Update DRAM configuration names blob | commitdiff | raw | diff to current
2016-10-13 Omar Najimem: add DRAM powerdown current blob | commitdiff | raw | diff to current
2016-10-13 Omar Najimem: update DDR3 die revision blob | commitdiff | raw | diff to current
2016-10-13 Omar Najimem: add DRAM powerdown timing blob | commitdiff | raw | diff to current
2016-10-13 Omar Najimem: make DDR4 x16 blob | commitdiff | raw | diff to current
2015-11-03 Erfan Azarkhishmem: hmc: minor fixes blob | commitdiff | raw | diff to current
2015-09-22 Wendy Elsassermem: Add initial HBM configurations blob | commitdiff | raw | diff to current
2015-07-03 Andreas Hanssonmem: Increase the default buffer sizes for the DDR4... blob | commitdiff | raw | diff to current
2015-06-07 Matthias Jungmem: Add HMC Timing Parameters blob | commitdiff | raw | diff to current
2015-02-03 Andreas Hanssonconfig: Adjust DRAM channel interleaving defaults blob | commitdiff | raw | diff to current
2014-12-02 Omar Najimem: Add a GDDR5 DRAM config blob | commitdiff | raw | diff to current
2014-11-14 Andreas Hanssonmem: Clarify unit of DRAM controller buffer size blob | commitdiff | raw | diff to current
2014-10-20 Omar Najimem: Add DRAM device size and check against config blob | commitdiff | raw | diff to current
2014-07-25 Omar Najimem: Add missig timing and current parameters to DRAM... blob | commitdiff | raw | diff to current
2014-10-09 Omar Najimem: Remove DRAMSim2 DDR3 configuration blob | commitdiff | raw | diff to current
2014-09-20 Wendy Elsassermem: Add DDR4 bank group timing blob | commitdiff | raw | diff to current
2014-09-20 Wendy Elsassermem: Add memory rank-to-rank delay blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Update DDR3 and DDR4 based on datasheets blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add DRAM cycle time blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add tRTP to the DRAM controller blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Add tWR to DRAM activate and precharge constraints blob | commitdiff | raw | diff to current
2014-05-09 Andreas Hanssonmem: Make DRAM read/write switching less conservative blob | commitdiff | raw | diff to current
2014-03-23 Andreas Hanssonmem: Rename SimpleDRAM to a more suitable DRAMCtrl blob | commitdiff | raw | diff to current