git.libre-soc.org Git - gem5.git/history

2015-09-22	Wendy Elsasser	mem: Add initial HBM configurations	blob \| commitdiff \| raw
2015-07-03	Andreas Hansson	mem: Increase the default buffer sizes for the DDR4...	blob \| commitdiff \| raw \| diff to current
2015-06-07	Matthias Jung	mem: Add HMC Timing Parameters	blob \| commitdiff \| raw \| diff to current
2015-02-03	Andreas Hansson	config: Adjust DRAM channel interleaving defaults	blob \| commitdiff \| raw \| diff to current
2014-12-02	Omar Naji	mem: Add a GDDR5 DRAM config	blob \| commitdiff \| raw \| diff to current
2014-11-14	Andreas Hansson	mem: Clarify unit of DRAM controller buffer size	blob \| commitdiff \| raw \| diff to current
2014-10-20	Omar Naji	mem: Add DRAM device size and check against config	blob \| commitdiff \| raw \| diff to current
2014-07-25	Omar Naji	mem: Add missig timing and current parameters to DRAM...	blob \| commitdiff \| raw \| diff to current
2014-10-09	Omar Naji	mem: Remove DRAMSim2 DDR3 configuration	blob \| commitdiff \| raw \| diff to current
2014-09-20	Wendy Elsasser	mem: Add DDR4 bank group timing	blob \| commitdiff \| raw \| diff to current
2014-09-20	Wendy Elsasser	mem: Add memory rank-to-rank delay	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Update DDR3 and DDR4 based on datasheets	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add DRAM cycle time	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add tRTP to the DRAM controller	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Add tWR to DRAM activate and precharge constraints	blob \| commitdiff \| raw \| diff to current
2014-05-09	Andreas Hansson	mem: Make DRAM read/write switching less conservative	blob \| commitdiff \| raw \| diff to current
2014-03-23	Andreas Hansson	mem: Rename SimpleDRAM to a more suitable DRAMCtrl	blob \| commitdiff \| raw \| diff to current

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