projects
/
gem5.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
riscv: Fix bugs with RISC-V decoder and detailed CPUs
[gem5.git]
/
src
/
mem
/
DRAMCtrl.py
2017-02-14
Wendy Elsasser
mem: Update DRAM configuration names
blob
|
commitdiff
|
raw
2016-10-13
Omar Naji
mem: add DRAM powerdown current
blob
|
commitdiff
|
raw
|
diff to current
2016-10-13
Omar Naji
mem: update DDR3 die revision
blob
|
commitdiff
|
raw
|
diff to current
2016-10-13
Omar Naji
mem: add DRAM powerdown timing
blob
|
commitdiff
|
raw
|
diff to current
2016-10-13
Omar Naji
mem: make DDR4 x16
blob
|
commitdiff
|
raw
|
diff to current
2015-11-03
Erfan Azarkhish
mem: hmc: minor fixes
blob
|
commitdiff
|
raw
|
diff to current
2015-09-22
Wendy Elsasser
mem: Add initial HBM configurations
blob
|
commitdiff
|
raw
|
diff to current
2015-07-03
Andreas Hansson
mem: Increase the default buffer sizes for the DDR4...
blob
|
commitdiff
|
raw
|
diff to current
2015-06-07
Matthias Jung
mem: Add HMC Timing Parameters
blob
|
commitdiff
|
raw
|
diff to current
2015-02-03
Andreas Hansson
config: Adjust DRAM channel interleaving defaults
blob
|
commitdiff
|
raw
|
diff to current
2014-12-02
Omar Naji
mem: Add a GDDR5 DRAM config
blob
|
commitdiff
|
raw
|
diff to current
2014-11-14
Andreas Hansson
mem: Clarify unit of DRAM controller buffer size
blob
|
commitdiff
|
raw
|
diff to current
2014-10-20
Omar Naji
mem: Add DRAM device size and check against config
blob
|
commitdiff
|
raw
|
diff to current
2014-07-25
Omar Naji
mem: Add missig timing and current parameters to DRAM...
blob
|
commitdiff
|
raw
|
diff to current
2014-10-09
Omar Naji
mem: Remove DRAMSim2 DDR3 configuration
blob
|
commitdiff
|
raw
|
diff to current
2014-09-20
Wendy Elsasser
mem: Add DDR4 bank group timing
blob
|
commitdiff
|
raw
|
diff to current
2014-09-20
Wendy Elsasser
mem: Add memory rank-to-rank delay
blob
|
commitdiff
|
raw
|
diff to current
2014-05-09
Andreas Hansson
mem: Update DDR3 and DDR4 based on datasheets
blob
|
commitdiff
|
raw
|
diff to current
2014-05-09
Andreas Hansson
mem: Add DRAM cycle time
blob
|
commitdiff
|
raw
|
diff to current
2014-05-09
Andreas Hansson
mem: Add tRTP to the DRAM controller
blob
|
commitdiff
|
raw
|
diff to current
2014-05-09
Andreas Hansson
mem: Add tWR to DRAM activate and precharge constraints
blob
|
commitdiff
|
raw
|
diff to current
2014-05-09
Andreas Hansson
mem: Make DRAM read/write switching less conservative
blob
|
commitdiff
|
raw
|
diff to current
2014-03-23
Andreas Hansson
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
blob
|
commitdiff
|
raw
|
diff to current