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mem: Add a simple adaptive version of the open-page policy
[gem5.git] / src / mem / SimpleDRAM.py
2013-11-01 Andreas Hanssonmem: Add a simple adaptive version of the open-page... blob | commitdiff | raw
2013-11-01 Neha Agarwalmem: Just-in-time write scheduling in DRAM controller blob | commitdiff | raw | diff to current
2013-11-01 Andreas Hanssonmem: Add tRRD as a timing parameter for the DRAM controller blob | commitdiff | raw | diff to current
2013-11-01 Andreas Hanssonmem: Less conservative tRAS in DRAM configurations blob | commitdiff | raw | diff to current
2013-11-01 Ani Udipimem: Add tRAS parameter to the DRAM controller model blob | commitdiff | raw | diff to current
2013-08-19 Andreas Hanssonconfig: Command line support for multi-channel memory blob | commitdiff | raw | diff to current
2013-08-19 Amin Farmahinimem: Replacing bytesPerCacheLine with DRAM burstLength... blob | commitdiff | raw | diff to current
2013-07-18 Andreas Hanssonmem: Set the cache line size on a system level blob | commitdiff | raw | diff to current
2013-05-30 Andreas Hanssonmem: More descriptive DRAM config names blob | commitdiff | raw | diff to current
2013-05-30 Andreas Hanssonmem: Add static latency to the DRAM controller blob | commitdiff | raw | diff to current
2013-05-30 Andreas Hanssonmem: Add a LPDDR3-1600 configuration blob | commitdiff | raw | diff to current
2013-05-30 Andreas Hanssonmem: Adapt the LPDDR2 to match a single x32 channel blob | commitdiff | raw | diff to current
2013-04-22 Andreas Hanssonmem: Address mapping with fine-grained channel interleaving blob | commitdiff | raw | diff to current
2013-04-22 Andreas Hanssonmem: More descriptive enum names for address mapping blob | commitdiff | raw | diff to current
2013-04-22 Andreas Hanssonmem: Add a WideIO DRAM configuration blob | commitdiff | raw | diff to current
2013-03-01 Andreas Hanssonmem: Add a method to build multi-channel DRAM configura... blob | commitdiff | raw | diff to current
2013-03-01 Andreas Hanssonmem: Add support for multi-channel DRAM configurations blob | commitdiff | raw | diff to current
2013-01-31 Andreas Hanssonmem: Add DDR3 and LPDDR2 DRAM controller configurations blob | commitdiff | raw | diff to current
2013-01-31 Ani Udipimem: Add tTAW and tFAW to the SimpleDRAM model blob | commitdiff | raw | diff to current
2012-11-02 Andreas Sandbergsim: Include object header files in SWIG interfaces blob | commitdiff | raw | diff to current
2012-09-21 Andreas HanssonDRAM: Introduce SimpleDRAM to capture a high-level... blob | commitdiff | raw | diff to current