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Fix a bug to handle the fact that a CPU can send Functional accesses while a sendTimi...
[gem5.git]
/
src
/
mem
/
cache
/
base_cache.cc
2006-08-15
Ron Dreslinski
Some changes to support blocking in the caches
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2006-07-19
Ali Saidi
Merge zizzer:/bk/newmem
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2006-07-18
Gabe Black
Merge m5.eecs.umich.edu:/bk/newmem
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2006-07-12
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-11
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-10
Ron Dreslinski
Merge zizzer:/z/m5/Bitkeeper/newmem
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2006-07-10
Ron Dreslinski
Some fixes so that MSHR's are matched and we don't...
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2006-07-07
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-07
Korey Sewell
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
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2006-07-07
Ron Dreslinski
Fix address range calculation. Still need bus to handl...
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2006-07-07
Korey Sewell
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
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2006-07-07
Ron Dreslinski
Update cpus to use the getPort function to use a connec...
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2006-07-07
Korey Sewell
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
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2006-07-07
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-06
Ron Dreslinski
Timing cache works for hello world test.
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2006-07-06
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-06
Ron Dreslinski
Merge zizzer:/z/m5/Bitkeeper/newmem
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2006-07-06
Ron Dreslinski
Now timing reads work in single level of cache with...
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2006-07-06
Ali Saidi
Merge zizzer:/bk/newmem
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2006-07-05
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-05
Kevin Lim
Merge ktlim@zizzer:/bk/newmem
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2006-07-01
Korey Sewell
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
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2006-06-30
Ron Dreslinski
First pass, now compiles with current head of tree.
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2006-06-30
Ron Dreslinski
Fix the packet data allocation methods. Small fixes...
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2006-06-30
Ron Dreslinski
Merge zizzer:/z/m5/Bitkeeper/newmem
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2006-06-28
Ron Dreslinski
Backing in more changsets, getting closer to compile
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2006-06-28
Ron Dreslinski
Was having difficulty with merging the cache, reverted...
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