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ruby: Replace Time with Cycles in SequencerMessage
[gem5.git]
/
src
/
mem
/
cache
/
cache_impl.hh
2013-01-07
Andreas Sandberg
mem: Fix guest corruption when caches handle uncacheabl...
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2013-01-07
Ali Saidi
cache: add note about where conflicts are handled
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2012-11-02
Andreas Sandberg
mem: Add support for writing back and flushing caches
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2012-10-15
Andreas Hansson
Mem: Use cycles to express cache-related latencies
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2012-09-25
Mrinmoy Ghosh
Cache: add a response latency to the caches
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2012-09-19
Andreas Hansson
AddrRange: Transition from Range<T> to AddrRange
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2012-09-11
Lena Olson
Cache: Split invalidateBlk up to seperate block vs...
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2012-08-22
Andreas Hansson
Packet: Remove NACKs from packet and its use in endpoints
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2012-08-22
Andreas Hansson
Port: Extend the QueuedPort interface and use where...
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2012-07-27
Anthony Gutierrez
cache: don't allow dirty data in the i-cache
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2012-07-09
Andreas Hansson
Port: Align port names in C++ and Python
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2012-07-09
Andreas Hansson
Port: Make getAddrRanges const
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2012-07-09
Andreas Hansson
Port: Add isSnooping to slave port (asking master port)
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2012-06-29
Dam Sunwoo
Mem: fix master id assertion in cache_impl.hh
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2012-06-29
Ali Saidi
Cache: Only invalidate a line in the cache when an...
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2012-06-07
Ali Saidi
mem: Delay deleting of incoming packets by one call.
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2012-06-05
Ali Saidi
sim: Remove FastAlloc
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2012-05-30
Andreas Hansson
Bus: Turn the PortId into a transport function parameter
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2012-05-30
Andreas Hansson
Packet: Unify the use of PortID in packet and port
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2012-05-10
Ali Saidi
Cache: restructure code that actually isn't a loop
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2012-05-10
Ali Saidi
Cache: Panic if you attempt to create a checkpoint...
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2012-05-01
Andreas Hansson
MEM: Separate requests and responses for timing accesses
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2012-04-14
Andreas Hansson
MEM: Remove the Broadcast destination from the packet
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2012-04-14
Andreas Hansson
MEM: Separate snoops and normal memory requests/responses
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2012-03-30
William Wang
MEM: Introduce the master/slave port sub-classes in C++
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2012-03-22
Andreas Hansson
MEM: Split SimpleTimingPort into PacketQueue and ports
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2012-03-09
Ali Saidi
cache: Allow main memory to be at disjoint address...
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2012-03-01
Ali Saidi
Cache: Fix an issue with LRU when bonus block is used...
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2012-02-24
Andreas Hansson
MEM: Simplify cache ports preparing for master/slave...
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2012-02-12
Dam Sunwoo
mem: fix cache stats to use request ids correctly
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2012-02-12
Ali Saidi
mem: Add a master ID to each request object.
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2012-02-12
Mrinmoy Ghosh
prefetcher: Make prefetcher a sim object instead of...
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2012-02-01
Gabe Black
Merge ... head, hopefully the last time for this batch.
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2012-01-31
Andreas Hansson
MEM: Remove the otherPort from the cache ports
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2012-01-28
Gabe Black
Merge with the main repo.
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2012-01-17
William Wang
MEM: Remove the functional ports from the memory system
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2012-01-17
Andreas Hansson
MEM: Separate queries for snooping and address ranges
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2012-01-17
Andreas Hansson
MEM: Remove Port removeConn and MemObject deletePortRefs
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2012-01-17
Andreas Hansson
MEM: Simplify ports by removing EventManager
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2012-01-17
Andreas Hansson
MEM: Differentiate functional cache accesses from CPU...
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2011-09-13
Ali Saidi
Prefetch: Don't prefetch if address is in the write...
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2011-08-19
Ali Saidi
Mem: Put prefetcher notify call before packet is deleted.
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2011-08-19
Ali Saidi
Prefetcher: Fix some memory leaks with the prefetcher.
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2011-07-15
Ali Saidi
Mem: Fix issue with prefetches originating at non-L1...
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2011-04-15
Nathan Binkert
trace: reimplement the DTRACE function so it doesn...
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2011-04-15
Nathan Binkert
includes: sort all includes
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2011-03-18
Ali Saidi
Automated merge with ssh://hg@repo.m5sim.org/m5
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2011-03-18
Ali Saidi
Mem: Fix issue with dirty block being lost when entire...
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2011-01-08
Steve Reinhardt
Replace curTick global variable with accessor functions.
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2010-10-18
Steve Reinhardt
cache: minor SC assertion fix
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2010-10-13
Gabe Black
Mem: Change the CLREX flag to CLEAR_LL.
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2010-09-22
Steve Reinhardt
cache: improve coherence handling of writebacks
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2010-09-09
Steve Reinhardt
cache: fail SC when invalidated while waiting for bus
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2010-09-09
Steve Reinhardt
mem: fix functional accesses to deal with coherence...
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2010-09-09
Steve Reinhardt
cache: coherence protocol enhancements & bug fixes
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2010-08-26
Steve Reinhardt
mem: fix m5.fast compile bug in previous cset
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2010-08-26
Steve Reinhardt
cache: fix a bug in atomic multilevel snoops
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2010-08-23
Gene Wu
MEM: Make CLREX a first class request operation and...
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2010-08-23
Gene Wu
ARM: Make sure that software prefetch instructions...
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2010-07-22
Timothy M. Jones
Port: Only indicate that a SimpleTimingPort is drained...
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2010-07-09
Steve Reinhardt
cache: fix bug in SC upgrade handling
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2010-06-23
Steve Reinhardt
cache: fix longstanding prefetcher bug
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2010-06-16
Steve Reinhardt
cache: fail store conditionals when upgrade loses race
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2010-06-16
Steve Reinhardt
cache: fix dirty bit setting
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2010-02-23
Lisa Hsu
cache: Make caches sharing aware and add occupancy...
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2010-01-22
Derek Hower
Automated merge with ssh://hg@m5sim.org/m5
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2010-01-19
Derek Hower
merge
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2010-01-18
Lisa Hsu
Automated merge with ssh://hsul@localhost:4444//repo/m5
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2010-01-12
Lisa Hsu
cache: make tags->insertBlock() and tags->accessBlock...
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2009-09-26
Steve Reinhardt
Minor cleanup: Use the blockAlign() method where it...
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2009-09-26
Steve Reinhardt
Force prefetches to check cache and MSHRs immediately...
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2009-08-03
Derek Hower
Automated merge with ssh://hg@m5sim.org/m5
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2009-08-02
Steve Reinhardt
Fix setting of INST_FETCH flag for O3 CPU.
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2009-05-17
Nathan Binkert
includes: sort includes again
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2009-05-17
Nathan Binkert
types: Move stuff for global types into src/base/types.hh
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2008-07-16
Steve Reinhardt
mem: use single BadAddr responder per system.
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2009-04-20
Gabe Black
Mem: Change isLlsc to isLLSC.
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2009-04-19
Gabe Black
Memory: Rename LOCKED for load locked store conditional...
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2009-04-06
Gabe Black
Merge ARM into the head. ARM will compile but may not...
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2009-03-12
Steve Reinhardt
cache: set dirty bit on swaps (oops!)
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2009-02-16
Steve Reinhardt
Fixes to get prefetching working again.
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2008-11-10
Steve Reinhardt
Cache: Refactor packet forwarding a bit.
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2008-11-04
Lisa Hsu
decouple eviction from insertion in the cache.
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2008-11-04
Lisa Hsu
Change the findBlock(addr, lat) to accessBlock, which...
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2008-11-04
Lisa Hsu
get rid of all instances of readTid() and getThreadNum...
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2008-10-09
Nathan Binkert
eventq: convert all usage of events to use the new...
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2008-06-28
Steve Reinhardt
Automated merge after backout.
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2008-06-28
Steve Reinhardt
Backed out changeset 94a7bb476fca: caused memory leak.
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2008-06-24
Ali Saidi
Automated merge with repo.m5sim.org/m5-stable
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2008-06-21
Steve Reinhardt
Generate more useful error messages for unconnected...
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2008-06-13
Steve Reinhardt
Automated merge with ssh://m5sim.org//repo/m5
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2008-06-13
Steve Reinhardt
Get rid of bogus cache assertion.
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2008-03-25
Steve Reinhardt
Automated merge with ssh://daystrom.m5sim.org//repo/m5
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2008-03-25
Steve Reinhardt
Fix handling of writeback-induced writebacks in atomic...
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2008-03-24
Steve Reinhardt
Don't FastAlloc MSHRs since we don't allocate them...
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2008-03-23
Steve Reinhardt
Fix cache problem with writes to tempBlock
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2008-03-17
Steve Reinhardt
Fix a few Packet memory leaks.
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2008-03-15
Steve Reinhardt
Fix subtle cache bug where read could return stale...
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2008-02-27
Steve Reinhardt
Automated merge with ssh://daystrom.m5sim.org//repo/m5
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2008-02-27
Steve Reinhardt
Revamp cache timing access mshr check to make stats...
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