git.libre-soc.org Git - gem5.git/history - src/mem/cache/cache

[gem5.git] / src / mem / cache / cache_impl.hh

2012-07-09	Andreas Hansson	Port: Make getAddrRanges const	blob \| commitdiff \| raw
2012-07-09	Andreas Hansson	Port: Add isSnooping to slave port (asking master port)	blob \| commitdiff \| raw \| diff to current
2012-06-29	Dam Sunwoo	Mem: fix master id assertion in cache_impl.hh	blob \| commitdiff \| raw \| diff to current
2012-06-29	Ali Saidi	Cache: Only invalidate a line in the cache when an...	blob \| commitdiff \| raw \| diff to current
2012-06-07	Ali Saidi	mem: Delay deleting of incoming packets by one call.	blob \| commitdiff \| raw \| diff to current
2012-06-05	Ali Saidi	sim: Remove FastAlloc	blob \| commitdiff \| raw \| diff to current
2012-05-30	Andreas Hansson	Bus: Turn the PortId into a transport function parameter	blob \| commitdiff \| raw \| diff to current
2012-05-30	Andreas Hansson	Packet: Unify the use of PortID in packet and port	blob \| commitdiff \| raw \| diff to current
2012-05-10	Ali Saidi	Cache: restructure code that actually isn't a loop	blob \| commitdiff \| raw \| diff to current
2012-05-10	Ali Saidi	Cache: Panic if you attempt to create a checkpoint...	blob \| commitdiff \| raw \| diff to current
2012-05-01	Andreas Hansson	MEM: Separate requests and responses for timing accesses	blob \| commitdiff \| raw \| diff to current
2012-04-14	Andreas Hansson	MEM: Remove the Broadcast destination from the packet	blob \| commitdiff \| raw \| diff to current
2012-04-14	Andreas Hansson	MEM: Separate snoops and normal memory requests/responses	blob \| commitdiff \| raw \| diff to current
2012-03-30	William Wang	MEM: Introduce the master/slave port sub-classes in C++	blob \| commitdiff \| raw \| diff to current
2012-03-22	Andreas Hansson	MEM: Split SimpleTimingPort into PacketQueue and ports	blob \| commitdiff \| raw \| diff to current
2012-03-09	Ali Saidi	cache: Allow main memory to be at disjoint address...	blob \| commitdiff \| raw \| diff to current
2012-03-01	Ali Saidi	Cache: Fix an issue with LRU when bonus block is used...	blob \| commitdiff \| raw \| diff to current
2012-02-24	Andreas Hansson	MEM: Simplify cache ports preparing for master/slave...	blob \| commitdiff \| raw \| diff to current
2012-02-12	Dam Sunwoo	mem: fix cache stats to use request ids correctly	blob \| commitdiff \| raw \| diff to current
2012-02-12	Ali Saidi	mem: Add a master ID to each request object.	blob \| commitdiff \| raw \| diff to current
2012-02-12	Mrinmoy Ghosh	prefetcher: Make prefetcher a sim object instead of...	blob \| commitdiff \| raw \| diff to current
2012-02-01	Gabe Black	Merge ... head, hopefully the last time for this batch.	blob \| commitdiff \| raw \| diff to current
2012-01-31	Andreas Hansson	MEM: Remove the otherPort from the cache ports	blob \| commitdiff \| raw \| diff to current
2012-01-28	Gabe Black	Merge with the main repo.	blob \| commitdiff \| raw \| diff to current
2012-01-17	William Wang	MEM: Remove the functional ports from the memory system	blob \| commitdiff \| raw \| diff to current
2012-01-17	Andreas Hansson	MEM: Separate queries for snooping and address ranges	blob \| commitdiff \| raw \| diff to current
2012-01-17	Andreas Hansson	MEM: Remove Port removeConn and MemObject deletePortRefs	blob \| commitdiff \| raw \| diff to current
2012-01-17	Andreas Hansson	MEM: Simplify ports by removing EventManager	blob \| commitdiff \| raw \| diff to current
2012-01-17	Andreas Hansson	MEM: Differentiate functional cache accesses from CPU...	blob \| commitdiff \| raw \| diff to current
2011-09-13	Ali Saidi	Prefetch: Don't prefetch if address is in the write...	blob \| commitdiff \| raw \| diff to current
2011-08-19	Ali Saidi	Mem: Put prefetcher notify call before packet is deleted.	blob \| commitdiff \| raw \| diff to current
2011-08-19	Ali Saidi	Prefetcher: Fix some memory leaks with the prefetcher.	blob \| commitdiff \| raw \| diff to current
2011-07-15	Ali Saidi	Mem: Fix issue with prefetches originating at non-L1...	blob \| commitdiff \| raw \| diff to current
2011-04-15	Nathan Binkert	trace: reimplement the DTRACE function so it doesn...	blob \| commitdiff \| raw \| diff to current
2011-04-15	Nathan Binkert	includes: sort all includes	blob \| commitdiff \| raw \| diff to current
2011-03-18	Ali Saidi	Automated merge with ssh://hg@repo.m5sim.org/m5	blob \| commitdiff \| raw \| diff to current
2011-03-18	Ali Saidi	Mem: Fix issue with dirty block being lost when entire...	blob \| commitdiff \| raw \| diff to current
2011-01-08	Steve Reinhardt	Replace curTick global variable with accessor functions.	blob \| commitdiff \| raw \| diff to current
2010-10-18	Steve Reinhardt	cache: minor SC assertion fix	blob \| commitdiff \| raw \| diff to current
2010-10-13	Gabe Black	Mem: Change the CLREX flag to CLEAR_LL.	blob \| commitdiff \| raw \| diff to current
2010-09-22	Steve Reinhardt	cache: improve coherence handling of writebacks	blob \| commitdiff \| raw \| diff to current
2010-09-09	Steve Reinhardt	cache: fail SC when invalidated while waiting for bus	blob \| commitdiff \| raw \| diff to current
2010-09-09	Steve Reinhardt	mem: fix functional accesses to deal with coherence...	blob \| commitdiff \| raw \| diff to current
2010-09-09	Steve Reinhardt	cache: coherence protocol enhancements & bug fixes	blob \| commitdiff \| raw \| diff to current
2010-08-26	Steve Reinhardt	mem: fix m5.fast compile bug in previous cset	blob \| commitdiff \| raw \| diff to current
2010-08-26	Steve Reinhardt	cache: fix a bug in atomic multilevel snoops	blob \| commitdiff \| raw \| diff to current
2010-08-23	Gene Wu	MEM: Make CLREX a first class request operation and...	blob \| commitdiff \| raw \| diff to current
2010-08-23	Gene Wu	ARM: Make sure that software prefetch instructions...	blob \| commitdiff \| raw \| diff to current
2010-07-22	Timothy M. Jones	Port: Only indicate that a SimpleTimingPort is drained...	blob \| commitdiff \| raw \| diff to current
2010-07-09	Steve Reinhardt	cache: fix bug in SC upgrade handling	blob \| commitdiff \| raw \| diff to current
2010-06-23	Steve Reinhardt	cache: fix longstanding prefetcher bug	blob \| commitdiff \| raw \| diff to current
2010-06-16	Steve Reinhardt	cache: fail store conditionals when upgrade loses race	blob \| commitdiff \| raw \| diff to current
2010-06-16	Steve Reinhardt	cache: fix dirty bit setting	blob \| commitdiff \| raw \| diff to current
2010-02-23	Lisa Hsu	cache: Make caches sharing aware and add occupancy...	blob \| commitdiff \| raw \| diff to current
2010-01-22	Derek Hower	Automated merge with ssh://hg@m5sim.org/m5	blob \| commitdiff \| raw \| diff to current
2010-01-19	Derek Hower	merge	blob \| commitdiff \| raw \| diff to current
2010-01-18	Lisa Hsu	Automated merge with ssh://hsul@localhost:4444//repo/m5	blob \| commitdiff \| raw \| diff to current
2010-01-12	Lisa Hsu	cache: make tags->insertBlock() and tags->accessBlock...	blob \| commitdiff \| raw \| diff to current
2009-09-26	Steve Reinhardt	Minor cleanup: Use the blockAlign() method where it...	blob \| commitdiff \| raw \| diff to current
2009-09-26	Steve Reinhardt	Force prefetches to check cache and MSHRs immediately...	blob \| commitdiff \| raw \| diff to current
2009-08-03	Derek Hower	Automated merge with ssh://hg@m5sim.org/m5	blob \| commitdiff \| raw \| diff to current
2009-08-02	Steve Reinhardt	Fix setting of INST_FETCH flag for O3 CPU.	blob \| commitdiff \| raw \| diff to current
2009-05-17	Nathan Binkert	includes: sort includes again	blob \| commitdiff \| raw \| diff to current
2009-05-17	Nathan Binkert	types: Move stuff for global types into src/base/types.hh	blob \| commitdiff \| raw \| diff to current
2008-07-16	Steve Reinhardt	mem: use single BadAddr responder per system.	blob \| commitdiff \| raw \| diff to current
2009-04-20	Gabe Black	Mem: Change isLlsc to isLLSC.	blob \| commitdiff \| raw \| diff to current
2009-04-19	Gabe Black	Memory: Rename LOCKED for load locked store conditional...	blob \| commitdiff \| raw \| diff to current
2009-04-06	Gabe Black	Merge ARM into the head. ARM will compile but may not...	blob \| commitdiff \| raw \| diff to current
2009-03-12	Steve Reinhardt	cache: set dirty bit on swaps (oops!)	blob \| commitdiff \| raw \| diff to current
2009-02-16	Steve Reinhardt	Fixes to get prefetching working again.	blob \| commitdiff \| raw \| diff to current
2008-11-10	Steve Reinhardt	Cache: Refactor packet forwarding a bit.	blob \| commitdiff \| raw \| diff to current
2008-11-04	Lisa Hsu	decouple eviction from insertion in the cache.	blob \| commitdiff \| raw \| diff to current
2008-11-04	Lisa Hsu	Change the findBlock(addr, lat) to accessBlock, which...	blob \| commitdiff \| raw \| diff to current
2008-11-04	Lisa Hsu	get rid of all instances of readTid() and getThreadNum...	blob \| commitdiff \| raw \| diff to current
2008-10-09	Nathan Binkert	eventq: convert all usage of events to use the new...	blob \| commitdiff \| raw \| diff to current
2008-06-28	Steve Reinhardt	Automated merge after backout.	blob \| commitdiff \| raw \| diff to current
2008-06-28	Steve Reinhardt	Backed out changeset 94a7bb476fca: caused memory leak.	blob \| commitdiff \| raw \| diff to current
2008-06-24	Ali Saidi	Automated merge with repo.m5sim.org/m5-stable	blob \| commitdiff \| raw \| diff to current
2008-06-21	Steve Reinhardt	Generate more useful error messages for unconnected...	blob \| commitdiff \| raw \| diff to current
2008-06-13	Steve Reinhardt	Automated merge with ssh://m5sim.org//repo/m5	blob \| commitdiff \| raw \| diff to current
2008-06-13	Steve Reinhardt	Get rid of bogus cache assertion.	blob \| commitdiff \| raw \| diff to current
2008-03-25	Steve Reinhardt	Automated merge with ssh://daystrom.m5sim.org//repo/m5	blob \| commitdiff \| raw \| diff to current
2008-03-25	Steve Reinhardt	Fix handling of writeback-induced writebacks in atomic...	blob \| commitdiff \| raw \| diff to current
2008-03-24	Steve Reinhardt	Don't FastAlloc MSHRs since we don't allocate them...	blob \| commitdiff \| raw \| diff to current
2008-03-23	Steve Reinhardt	Fix cache problem with writes to tempBlock	blob \| commitdiff \| raw \| diff to current
2008-03-17	Steve Reinhardt	Fix a few Packet memory leaks.	blob \| commitdiff \| raw \| diff to current
2008-03-15	Steve Reinhardt	Fix subtle cache bug where read could return stale...	blob \| commitdiff \| raw \| diff to current
2008-02-27	Steve Reinhardt	Automated merge with ssh://daystrom.m5sim.org//repo/m5	blob \| commitdiff \| raw \| diff to current
2008-02-27	Steve Reinhardt	Revamp cache timing access mshr check to make stats...	blob \| commitdiff \| raw \| diff to current
2008-02-27	Steve Reinhardt	Cache: better comments particularly regarding writeback...	blob \| commitdiff \| raw \| diff to current
2008-02-16	Steve Reinhardt	Make L2+ caches allocate new block for writeback misses	blob \| commitdiff \| raw \| diff to current
2008-02-11	Steve Reinhardt	Automated merge with file:/home/stever/hg/m5-orig	blob \| commitdiff \| raw \| diff to current
2008-02-10	Steve Reinhardt	Fix #include lines for renamed cache files.	blob \| commitdiff \| raw \| diff to current
2008-01-06	Geoffrey Blake	Temporary fix for ll/sc bug see flyspray task for more...	blob \| commitdiff \| raw \| diff to current
2008-01-02	Steve Reinhardt	Add ReadRespWithInvalidate to handle multi-level cohere...	blob \| commitdiff \| raw \| diff to current
2008-01-02	Steve Reinhardt	Don't DPRINTF in the middle of a PrintReq.	blob \| commitdiff \| raw \| diff to current
2008-01-02	Steve Reinhardt	Add functional PrintReq command for memory-system debug...	blob \| commitdiff \| raw \| diff to current
2008-01-02	Steve Reinhardt	Fix formatting and comments in cache_impl.hh	blob \| commitdiff \| raw \| diff to current
2007-11-20	Gabe Black	Merge with head.	blob \| commitdiff \| raw \| diff to current
2007-11-17	Steve Reinhardt	Tweak check for writable block fill.	blob \| commitdiff \| raw \| diff to current
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