git.libre-soc.org Git - gem5.git/history - src/mem/cache/prefetch/Prefetcher.py

2018-11-15	Daniel	mem-cache: Make StridePrefetcher use Replacement Policies	blob \| commitdiff \| raw
2018-11-15	Daniel	mem-cache: Cleanup prefetchers	blob \| commitdiff \| raw \| diff to current
2018-11-14	Javier Bueno	mem-cache: implement a probe-based interface	blob \| commitdiff \| raw \| diff to current
2014-12-23	Mitch Hayenga	mem: Rework the structuring of the prefetchers	blob \| commitdiff \| raw \| diff to current
2014-10-16	Andreas Hansson	mem: Dynamically determine page bytes in memory components	blob \| commitdiff \| raw \| diff to current
2014-09-20	Mitch Hayenga	mem: Remove the GHB prefetcher from the source tree	blob \| commitdiff \| raw \| diff to current
2014-01-30	Mitch Hayenga	mem: Allowed tagged instruction prefetching in stride...	blob \| commitdiff \| raw \| diff to current
2014-01-30	Mitch Hayenga ext...	mem: prefetcher: add options, support for unaligned...	blob \| commitdiff \| raw \| diff to current
2012-11-02	Andreas Sandberg	sim: Include object header files in SWIG interfaces	blob \| commitdiff \| raw \| diff to current
2012-10-15	Andreas Hansson	Mem: Use cycles to express cache-related latencies	blob \| commitdiff \| raw \| diff to current
2012-02-12	Ali Saidi	mem: Add a master ID to each request object.	blob \| commitdiff \| raw \| diff to current
2012-02-12	Mrinmoy Ghosh	prefetcher: Make prefetcher a sim object instead of...	blob \| commitdiff \| raw \| diff to current