Port: Make getAddrRanges const
[gem5.git] / src / mem / cache /
2012-07-09 Andreas HanssonPort: Make getAddrRanges const
2012-07-09 Andreas HanssonPort: Add isSnooping to slave port (asking master port)
2012-07-09 Andreas HanssonPort: Move retry from port base class to Master/SlavePort
2012-07-09 Andreas HanssonFix: Address a few benign memory leaks
2012-06-29 Lena OlsonCache: Fix the LRU policy for classic memory hierarchy
2012-06-29 Dam SunwooMem: fix master id assertion in cache_impl.hh
2012-06-29 Ali SaidiCache: Only invalidate a line in the cache when an...
2012-06-07 Ali Saidimem: Delay deleting of incoming packets by one call.
2012-06-05 Ali Saidisim: Remove FastAlloc
2012-05-30 Andreas HanssonBus: Turn the PortId into a transport function parameter
2012-05-30 Andreas HanssonPacket: Unify the use of PortID in packet and port
2012-05-24 Andreas HanssonCache: Remove dangling doWriteback declaration
2012-05-10 Ali SaidiCache: restructure code that actually isn't a loop
2012-05-10 Ali Saidigem5: fix some iterator use and erase bugs
2012-05-10 Ali Saidigem5: Fix a number of incorrect case statements
2012-05-10 Ali SaidiCache: Panic if you attempt to create a checkpoint...
2012-05-01 Andreas HanssonMEM: Separate requests and responses for timing accesses
2012-04-14 Andreas HanssonMEM: Remove the Broadcast destination from the packet
2012-04-14 Andreas HanssonMEM: Separate snoops and normal memory requests/responses
2012-04-06 Andreas HanssonMEM: Enable multiple distributed generalized memories
2012-03-30 William WangMEM: Introduce the master/slave port sub-classes in C++
2012-03-22 Andreas HanssonMEM: Split SimpleTimingPort into PacketQueue and ports
2012-03-09 Ali Saidicache: Allow main memory to be at disjoint address...
2012-03-01 Ali SaidiCache: Fix an issue with LRU when bonus block is used...
2012-02-24 Andreas HanssonMEM: Simplify cache ports preparing for master/slave...
2012-02-13 Andreas HanssonMEM: Introduce the master/slave port roles in the Pytho...
2012-02-12 Dam Sunwoomem: fix cache stats to use request ids correctly
2012-02-12 Ali Saidimem: Add a master ID to each request object.
2012-02-12 Mrinmoy Ghoshprefetcher: Make prefetcher a sim object instead of...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Koan-Sin Tanclang: Enable compiling gem5 using clang 2.9 and 3.0
2012-01-31 Andreas HanssonMEM: Remove the otherPort from the cache ports
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-17 William WangMEM: Remove the functional ports from the memory system
2012-01-17 Andreas HanssonMEM: Separate queries for snooping and address ranges
2012-01-17 Andreas HanssonMEM: Remove Port removeConn and MemObject deletePortRefs
2012-01-17 Andreas HanssonMEM: Simplify ports by removing EventManager
2012-01-17 Andreas HanssonMEM: Differentiate functional cache accesses from CPU...
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-18 Gabe BlackSE/FS: Get rid of includes of config/full_system.hh.
2011-11-07 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in mem.
2011-10-31 Gabe BlackGCC: Get everything working with gcc 4.6.1.
2011-09-13 Ali SaidiPrefetch: Don't prefetch if address is in the write...
2011-09-01 Lisa HsuFix build for gcc-4.2 opt/fast
2011-08-19 Ali SaidiMem: Put prefetcher notify call before packet is deleted.
2011-08-19 Ali SaidiPrefetcher: Fix some memory leaks with the prefetcher.
2011-07-15 Ali SaidiMem: Fix issue with prefetches originating at non-L1...
2011-06-03 Nathan Binkertscons: rename TraceFlags to DebugFlags
2011-04-20 Nathan Binkertstats: rename stats so they can be used as python expre...
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiMem: Fix issue with dirty block being lost when entire...
2011-02-23 Ali SaidiIncludes: Don't include isa_traits.hh and use the TheIS...
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-11-20 Ali SaidiSCons: Support building without an ISA
2010-10-18 Steve Reinhardtcache: minor SC assertion fix
2010-10-13 Gabe BlackMem: Change the CLREX flag to CLEAR_LL.
2010-09-22 Steve Reinhardtcache: improve coherence handling of writebacks
2010-09-10 Nathan Binkertstyle: fix sorting of includes and whitespace in some...
2010-09-09 Steve Reinhardtcache: fail SC when invalidated while waiting for bus
2010-09-09 Steve Reinhardtmem: fix functional accesses to deal with coherence...
2010-09-09 Steve Reinhardtcache: coherence protocol enhancements & bug fixes
2010-08-26 Steve Reinhardtmem: fix m5.fast compile bug in previous cset
2010-08-26 Steve Reinhardtcache: fix a bug in atomic multilevel snoops
2010-08-25 Steve Reinhardtmem: fix dumb typo in copyrights
2010-08-23 Gene WuMEM: Make CLREX a first class request operation and...
2010-08-23 Gene WuARM: Make sure that software prefetch instructions...
2010-08-23 Ali SaidiCompiler: Fixes for GCC 4.5.
2010-07-22 Timothy M. JonesPort: Only indicate that a SimpleTimingPort is drained...
2010-07-09 Steve Reinhardtcache: fix bug in SC upgrade handling
2010-06-23 Steve Reinhardtcache: fix longstanding prefetcher bug
2010-06-16 Steve Reinhardtcache: fail store conditionals when upgrade loses race
2010-06-16 Steve Reinhardtcache: fix dirty bit setting
2010-06-15 Nathan Binkertstats: only consider a formula initialized if there...
2010-02-24 Lisa Hsucache stats: account for writebacks and/or device occup...
2010-02-23 Lisa Hsucache: Make caches sharing aware and add occupancy...
2010-02-23 Lisa Hsucache: pull CacheSet out of LRU so that other tags...
2010-01-22 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2010-01-19 Derek Howermerge
2010-01-18 Lisa HsuAutomated merge with ssh://hsul@localhost:4444//repo/m5
2010-01-12 Lisa Hsucache: make tags->insertBlock() and tags->accessBlock...
2009-09-26 Steve ReinhardtMinor cleanup: Use the blockAlign() method where it...
2009-09-26 Steve ReinhardtForce prefetches to check cache and MSHRs immediately...
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtFix setting of INST_FETCH flag for O3 CPU.
2009-06-05 Nathan Binkerttypes: clean up types, especially signed vs unsigned
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-05-17 Nathan Binkertincludes: sort includes again
2009-05-17 Nathan Binkertincludes: use base/types.hh not inttypes.h or stdint.h
2009-05-17 Nathan Binkerttypes: Move stuff for global types into src/base/types.hh
2008-07-16 Steve Reinhardtmem: use single BadAddr responder per system.
2009-04-21 Steve Reinhardtrequest: rename INST_READ to INST_FETCH.
2009-04-20 Gabe BlackMem: Change isLlsc to isLLSC.
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