Ruby: Add infrastructure for recording cache contents
[gem5.git] / src / mem / cache /
2011-10-31 Gabe BlackGCC: Get everything working with gcc 4.6.1.
2011-09-13 Ali SaidiPrefetch: Don't prefetch if address is in the write...
2011-09-01 Lisa HsuFix build for gcc-4.2 opt/fast
2011-08-19 Ali SaidiMem: Put prefetcher notify call before packet is deleted.
2011-08-19 Ali SaidiPrefetcher: Fix some memory leaks with the prefetcher.
2011-07-15 Ali SaidiMem: Fix issue with prefetches originating at non-L1...
2011-06-03 Nathan Binkertscons: rename TraceFlags to DebugFlags
2011-04-20 Nathan Binkertstats: rename stats so they can be used as python expre...
2011-04-15 Nathan Binkerttrace: reimplement the DTRACE function so it doesn...
2011-04-15 Nathan Binkertincludes: sort all includes
2011-03-18 Ali SaidiAutomated merge with ssh://hg@repo.m5sim.org/m5
2011-03-18 Ali SaidiMem: Fix issue with dirty block being lost when entire...
2011-02-23 Ali SaidiIncludes: Don't include isa_traits.hh and use the TheIS...
2011-01-08 Steve ReinhardtReplace curTick global variable with accessor functions.
2010-11-20 Ali SaidiSCons: Support building without an ISA
2010-10-18 Steve Reinhardtcache: minor SC assertion fix
2010-10-13 Gabe BlackMem: Change the CLREX flag to CLEAR_LL.
2010-09-22 Steve Reinhardtcache: improve coherence handling of writebacks
2010-09-10 Nathan Binkertstyle: fix sorting of includes and whitespace in some...
2010-09-09 Steve Reinhardtcache: fail SC when invalidated while waiting for bus
2010-09-09 Steve Reinhardtmem: fix functional accesses to deal with coherence...
2010-09-09 Steve Reinhardtcache: coherence protocol enhancements & bug fixes
2010-08-26 Steve Reinhardtmem: fix m5.fast compile bug in previous cset
2010-08-26 Steve Reinhardtcache: fix a bug in atomic multilevel snoops
2010-08-25 Steve Reinhardtmem: fix dumb typo in copyrights
2010-08-23 Gene WuMEM: Make CLREX a first class request operation and...
2010-08-23 Gene WuARM: Make sure that software prefetch instructions...
2010-08-23 Ali SaidiCompiler: Fixes for GCC 4.5.
2010-07-22 Timothy M. JonesPort: Only indicate that a SimpleTimingPort is drained...
2010-07-09 Steve Reinhardtcache: fix bug in SC upgrade handling
2010-06-23 Steve Reinhardtcache: fix longstanding prefetcher bug
2010-06-16 Steve Reinhardtcache: fail store conditionals when upgrade loses race
2010-06-16 Steve Reinhardtcache: fix dirty bit setting
2010-06-15 Nathan Binkertstats: only consider a formula initialized if there...
2010-02-24 Lisa Hsucache stats: account for writebacks and/or device occup...
2010-02-23 Lisa Hsucache: Make caches sharing aware and add occupancy...
2010-02-23 Lisa Hsucache: pull CacheSet out of LRU so that other tags...
2010-01-22 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2010-01-19 Derek Howermerge
2010-01-18 Lisa HsuAutomated merge with ssh://hsul@localhost:4444//repo/m5
2010-01-12 Lisa Hsucache: make tags->insertBlock() and tags->accessBlock...
2009-09-26 Steve ReinhardtMinor cleanup: Use the blockAlign() method where it...
2009-09-26 Steve ReinhardtForce prefetches to check cache and MSHRs immediately...
2009-09-23 Nathan Binkertarch: nuke arch/isa_specific.hh and move stuff to gener...
2009-08-03 Derek HowerAutomated merge with ssh://hg@m5sim.org/m5
2009-08-02 Steve ReinhardtFix setting of INST_FETCH flag for O3 CPU.
2009-06-05 Nathan Binkerttypes: clean up types, especially signed vs unsigned
2009-05-26 Nathan Binkerttypes: add a type for thread IDs and try to use it...
2009-05-17 Nathan Binkertincludes: sort includes again
2009-05-17 Nathan Binkertincludes: use base/types.hh not inttypes.h or stdint.h
2009-05-17 Nathan Binkerttypes: Move stuff for global types into src/base/types.hh
2008-07-16 Steve Reinhardtmem: use single BadAddr responder per system.
2009-04-21 Steve Reinhardtrequest: rename INST_READ to INST_FETCH.
2009-04-20 Gabe BlackMem: Change isLlsc to isLLSC.
2009-04-19 Gabe BlackMemory: Rename LOCKED for load locked store conditional...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-03-12 Steve Reinhardtcache: set dirty bit on swaps (oops!)
2009-03-11 Steve Reinhardtprefetch: don't panic on requests w/o contextID (e...
2009-03-06 Nathan Binkertstats: Fix all stats usages to deal with template fixes
2009-02-16 Steve ReinhardtFixes to get prefetching working again.
2008-11-14 Steve ReinhardtCache: get rid of obsolete Tag methods.
2008-11-10 Steve ReinhardtCache: Refactor packet forwarding a bit.
2008-11-04 Lisa Hsudecouple eviction from insertion in the cache.
2008-11-04 Lisa HsuChange the findBlock(addr, lat) to accessBlock, which...
2008-11-04 Lisa Hsuget rid of all instances of readTid() and getThreadNum...
2008-11-03 Lisa HsuAdd in Context IDs to the simulator. From now on,...
2008-10-23 Lisa Hsus/cpu_id/cpuId in o3 (to be consistent and match style...
2008-10-23 Lisa Hsuprobe function no longer used anywhere.
2008-10-23 Lisa Hsuremove the totally obsolete split cache
2008-10-20 Lisa HsuAutomated merge with ssh://daystrom.m5sim.org//z/repo/m5
2008-10-16 Lisa HsuAutomated merge with ssh://daystrom.m5sim.org//z/repo/m5
2008-10-14 Lisa HsuThis function declaration isn't used anywhere.
2008-10-09 Nathan Binkerteventq: convert all usage of events to use the new...
2008-09-10 Ali Saidistyle: Remove non-leading tabs everywhere they shouldn...
2008-06-28 Steve ReinhardtAutomated merge after backout.
2008-06-28 Steve ReinhardtBacked out changeset 94a7bb476fca: caused memory leak.
2008-06-24 Ali SaidiAutomated merge with repo.m5sim.org/m5-stable
2008-06-21 Steve ReinhardtGenerate more useful error messages for unconnected...
2008-06-13 Steve ReinhardtAutomated merge with ssh://m5sim.org//repo/m5
2008-06-13 Steve ReinhardtGet rid of bogus cache assertion.
2008-05-15 Ali SaidiMake sure that output files are always checked success...
2008-03-25 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-03-25 Steve ReinhardtFix handling of writeback-induced writebacks in atomic...
2008-03-24 Steve ReinhardtDon't FastAlloc MSHRs since we don't allocate them...
2008-03-23 Steve ReinhardtFix cache problem with writes to tempBlock
2008-03-17 Steve ReinhardtFix a few Packet memory leaks.
2008-03-15 Steve ReinhardtFix subtle cache bug where read could return stale...
2008-02-27 Steve ReinhardtAutomated merge with ssh://daystrom.m5sim.org//repo/m5
2008-02-27 Steve ReinhardtRevamp cache timing access mshr check to make stats...
2008-02-27 Steve ReinhardtCache: better comments particularly regarding writeback...
2008-02-16 Steve ReinhardtMake L2+ caches allocate new block for writeback misses
2008-02-11 Steve ReinhardtAutomated merge with file:/home/stever/hg/m5-orig
2008-02-10 Steve ReinhardtFix #include lines for renamed cache files.
2008-02-10 Steve ReinhardtRename cache files for brevity and consistency with...
2008-01-06 Geoffrey BlakeTemporary fix for ll/sc bug see flyspray task for more...
2008-01-02 Steve ReinhardtAdd ReadRespWithInvalidate to handle multi-level cohere...
2008-01-02 Steve ReinhardtMark cache-to-cache MSHRs as downstreamPending when...
2008-01-02 Steve ReinhardtDon't DPRINTF in the middle of a PrintReq.
2008-01-02 Steve ReinhardtAdditional comments and helper functions for PrintReq.
2008-01-02 Steve ReinhardtAdd functional PrintReq command for memory-system debug...
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