cpu: Apply the ARM TLB rework to the O3 checker CPU.
[gem5.git] / src / mem / dram_ctrl.cc
2019-10-03 Tommaso Marinellimem: Remove unused variable
2019-09-30 Andreas Sandbergmem: Convert DRAM controller to new-style stats
2019-06-06 Matthew Porembamem: Option to toggle DRAM low-power states
2019-04-28 Gabe Blackmem: Minimize the use of MemObject.
2019-04-19 Daniel R. Carvalhomem: Make DRAMCtrl::decodeAddr const
2019-04-05 Jason Lowe-Powermem: Reverse order of write/read mem queue check
2019-03-19 Gabe Blackarch, cpu, dev, gpu, mem, sim, python: start using...
2019-01-17 Nikos Nikolerismem: Determine if a packet queue forces ordering at...
2018-09-07 Matteo Andreozzimem: Make DRAMCtrl a QoS-aware Memory Controller
2018-07-23 Robert Kovacsicsmem: Rename Packet::checkFunctional to trySatisfyFunctional
2018-05-18 Wendy Elsassermem: Add support for more flexible DRAM timing and...
2018-05-18 Wendy Elsassermem: Optimize self-refresh entry
2018-04-06 Daniel R. Carvalhomem: Remove unused 'using namespace'
2017-11-16 Radhika Jagtapext, mem: Pull DRAMPower SHA 90d6290 and rebase
2017-06-20 Sean Wilsonmem: Replace EventWrapper use with EventFunctionWrapper
2017-06-20 Sean Wilsonmem: Move the Rank construction logic to the Rank const...
2017-02-15 Wendy Elsassermem: fix assertion in respondEvent
2016-11-09 Brandon Potterstyle: [patch 1/22] use /r/3648/ to reorganize includes
2016-10-13 Wendy Elsassermem: Add DRAM low-power functionality
2016-10-13 Wendy Elsassermem: Add callback to compute stats prior to dump event
2016-10-13 Wendy Elsassermem: Modify drain to ensure banks and power are idled
2016-10-13 Wendy Elsassermem: Sort memory commands and update DRAMPower
2016-10-13 Omar Najimem: add DRAM powerdown timing
2016-02-10 Andreas Hanssonmem: Move the point of coherency to the coherent crossbar
2016-02-07 Steve Reinhardtstyle: fix missing spaces in control statements
2015-12-31 Andreas Hanssonmem: Make cache terminology easier to understand
2015-11-06 Ali Jafrimem: Enforce insertion order on the cache response...
2015-11-06 Andreas Hanssonmem: Align rules for sinking inhibited packets at the...
2015-11-06 Andreas Hanssonmem: Unify delayed packet deletion
2015-11-06 Andreas Hanssonmisc: Appease clang static analyzer
2015-07-07 Andreas Sandbergsim: Refactor and simplify the drain API
2015-07-07 Andreas Sandbergsim: Decouple draining from the SimObject hierarchy
2015-07-07 Andreas Sandbergsim: Make the drain state a global typed enum
2015-07-03 Wendy Elsassermem: Update DRAM command scheduler for bank groups
2015-07-03 Andreas Hanssonmem: Avoid DRAM write queue iteration for merging and...
2015-07-03 Ali Jafrimem: Add clean evicts to improve snoop filter tracking
2015-04-30 Rizwana Begummem: Simplify page close checks for adaptive policies
2015-03-02 Marco Balbonimem: Downstream components consumes new crossbar delays
2015-03-02 Andreas Hanssonmem: Split port retry for all different packet classes
2015-02-11 Marco Balbonimem: Clarification of packet crossbar timings
2015-01-20 Andreas Hanssonmem: Move DRAM interleaving check to init
2014-12-23 Andreas Hanssonconfig: Expose the DRAM ranks as a command-line option
2014-12-23 Andreas Hanssonmem: Ensure DRAM controller is idle when in atomic...
2014-12-23 Omar Najimem: Add rank-wise refresh to the DRAM controller
2014-12-23 Omar Najimem: Fix a bug in the DRAM controller arbitration
2014-12-02 Omar Najimem: Add a GDDR5 DRAM config
2014-10-30 Ali Saidiautomated merge
2014-10-30 Ali Saidiarm, mem: Fix drain bug and provide drain prints for...
2014-10-20 Omar Najimem: Fix DRAM activationlLimit bug
2014-10-20 Omar Najimem: Add DRAM device size and check against config
2014-10-16 Andreas Hanssonmem: Dynamically determine page bytes in memory components
2014-07-29 Omar Najimem: DRAMPower integration for on-line DRAM power stats
2014-09-20 Andreas Hanssonmem: Rename Bus to XBar to better reflect its behaviour
2014-09-20 Wendy Elsassermem: Add DDR4 bank group timing
2014-09-20 Wendy Elsassermem: Add memory rank-to-rank delay
2014-08-26 Andreas Hanssonmem: Fix address interleaving bug in DRAM controller
2014-06-30 Andreas Hanssonmem: DRAMPower trace output
2014-06-30 Andreas Hanssonmem: Add bank and rank indices as fields to the DRAM...
2014-06-30 Andreas Hanssonmem: Extend DRAM row bits from 16 to 32 for larger...
2014-05-09 Andreas Hanssonmem: Add DRAM cycle time
2014-05-09 Andreas Hanssonmem: Simplify DRAM response scheduling
2014-05-09 Andreas Hanssonmem: Add precharge all (PREA) to the DRAM controller
2014-05-09 Andreas Hanssonmem: Remove printing of DRAM params
2014-05-09 Andreas Hanssonmem: Add tRTP to the DRAM controller
2014-05-09 Andreas Hanssonmem: Merge DRAM latency calculation and bank state...
2014-05-09 Andreas Hanssonmem: Add tWR to DRAM activate and precharge constraints
2014-05-09 Andreas Hanssonmem: Merge DRAM page-management calculations
2014-05-09 Andreas Hanssonmem: Add DRAM power states to the controller
2014-05-09 Andreas Hanssonmem: Ensure DRAM refresh respects timings
2014-05-09 Andreas Hanssonmem: Make DRAM read/write switching less conservative
2014-03-23 Andreas Hanssonmem: Track DRAM read/write switching and add hysteresis
2014-03-23 Andreas Hanssonmem: Rename SimpleDRAM to a more suitable DRAMCtrl