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mem-cache: Create an address aware TempCacheBlk
[gem5.git]
/
src
/
mem
/
dram_ctrl.hh
2018-05-18
Wendy Elsasser
mem: Add support for more flexible DRAM timing and...
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2018-05-18
Wendy Elsasser
mem: Optimize self-refresh entry
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2017-11-16
Radhika Jagtap
ext, mem: Pull DRAMPower SHA 90d6290 and rebase
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2017-06-20
Sean Wilson
mem: Replace EventWrapper use with EventFunctionWrapper
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2017-06-20
Sean Wilson
mem: Move the Rank construction logic to the Rank const...
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2016-10-13
Wendy Elsasser
mem: Add DRAM low-power functionality
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2016-10-13
Wendy Elsasser
mem: Add callback to compute stats prior to dump event
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2016-10-13
Wendy Elsasser
mem: Modify drain to ensure banks and power are idled
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2016-10-13
Wendy Elsasser
mem: Sort memory commands and update DRAMPower
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2016-10-13
Omar Naji
mem: add DRAM powerdown timing
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2016-07-01
Jason Lowe-Power
misc: merge with sytle checker fix
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2016-07-01
Matthias Jung
ext: Update DRAMPower
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2015-11-06
Andreas Hansson
mem: Unify delayed packet deletion
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2015-10-12
Andreas Hansson
misc: Add explicit overrides and fix other clang >...
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2015-10-12
Andreas Hansson
misc: Remove redundant compiler-specific defines
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2015-07-07
Andreas Sandberg
sim: Refactor and simplify the drain API
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2015-07-03
Wendy Elsasser
mem: Update DRAM command scheduler for bank groups
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2015-07-03
Andreas Hansson
mem: Avoid DRAM write queue iteration for merging and...
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2015-03-02
Andreas Hansson
mem: Split port retry for all different packet classes
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2014-12-23
Andreas Hansson
mem: Ensure DRAM controller is idle when in atomic...
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2014-12-23
Omar Naji
mem: Add rank-wise refresh to the DRAM controller
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2014-10-20
Omar Naji
mem: Add DRAM device size and check against config
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2014-07-29
Omar Naji
mem: DRAMPower integration for on-line DRAM power stats
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2014-09-20
Wendy Elsasser
mem: Add DDR4 bank group timing
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2014-09-20
Wendy Elsasser
mem: Add memory rank-to-rank delay
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2014-08-26
Andreas Hansson
mem: Update DRAM controller comments
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2014-08-26
Andreas Hansson
mem: Fix address interleaving bug in DRAM controller
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2014-06-30
Andreas Hansson
mem: DRAMPower trace output
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2014-06-30
Andreas Hansson
mem: Add bank and rank indices as fields to the DRAM...
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2014-06-30
Andreas Hansson
mem: Extend DRAM row bits from 16 to 32 for larger...
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2014-05-09
Andreas Hansson
mem: Add DRAM cycle time
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2014-05-09
Andreas Hansson
mem: Simplify DRAM response scheduling
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2014-05-09
Andreas Hansson
mem: Remove printing of DRAM params
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2014-05-09
Andreas Hansson
mem: Add tRTP to the DRAM controller
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2014-05-09
Andreas Hansson
mem: Merge DRAM latency calculation and bank state...
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2014-05-09
Andreas Hansson
mem: Add tWR to DRAM activate and precharge constraints
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2014-05-09
Andreas Hansson
mem: Add DRAM power states to the controller
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2014-05-09
Andreas Hansson
mem: Ensure DRAM refresh respects timings
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2014-05-09
Andreas Hansson
mem: Make DRAM read/write switching less conservative
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2014-03-23
Andreas Hansson
mem: Track DRAM read/write switching and add hysteresis
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2014-03-23
Andreas Hansson
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
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